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Lab 3: Adding Custom IP to an
Embedded System Lab
Targeting MicroBlaze™ on Spartan™-3E Starter Kit
Adding Custom IP Lab: www.xilinx.com/univ 3-1
MicroBlaze Processor xup@xilinx.com
Lab 3: Adding Custom IP to an Embedded System
Introduction
This lab guides you through the process of adding a custom peripheral to a processor system by
using the Create and Import Peripheral Wizard.
Objectives
After completing this lab, you will be able to:
• Create a custom peripheral and import it to the IP catalog
• Add the custom peripheral to your design
• Add pin location constraints
• Generate the bitstream and verify operation in hardware
Procedure
You will extend the Lab 2 hardware design by creating and adding a PLB peripheral (refer to
MYIP in Figure 3-1) to the system, and connecting it to the LCD on the Spartan-3E kit. You
will use the Create and Import Peripheral Wizard of Xilinx Platform Studio (XPS) to generate
the peripheral templates. You will complete the peripheral by adding LCD interface logic in the
templates. Next, you will connect the peripheral to the system and add pin location constraints
to connect the LCD controller peripheral to the on-board LCD. Finally, you will verify
operation in hardware using the provided software application.
This lab comprises the following steps:
1. Open the project
2. Generate a peripheral template
3. Create a peripheral
4. Add and connect the peripheral
5. Verify the design in hardware
Adding Custom IP Lab: www.xilinx.com/univ 3-2
MicroBlaze Processor xup@xilinx.com
Figure 3-1. Design updated from previous lab
For each procedure within a primary step, there are general instructions (indicated by the
symbol). These general instructions only provide a broad outline for performing the
procedure. Below these general instructions, you will find accompanying step-by-step
directions and illustrated figures that provide more detail for performing the procedure. If you
feel confident about completing a procedure, you can skip the step-by-step directions and
move on to the next general instruction.
LMB
BRAM
CNTLR
LMB
BRAM
CNTLR
BRAM
PLB
MDM
UART
MicroBlaze
GPIO
GPIO
PSB
LEDs
LCD
MYIP
GPIO
DIP
MPMC
CNTLR
DDR
Adding Custom IP Lab: www.xilinx.com/univ 3-3
MicroBlaze Processor xup@xilinx.com
Opening the Project Step 1
Create a lab3 folder and copy the contents of the lab2 folder into the lab3 folder
if you wish to continue with the design you created in the previous lab,
otherwise copy the lab2 folder content from the completed folder into the lab3
folder. Open the project in XPS.
If you wish to continue using the design that you created in Lab 2, create a lab3 folder in
the c:\xup\embedded\labs directory and copy the contents from lab2 to lab3, otherwise
copy the content of lab2 folder from the completed folder
Open XPS by clicking Start →
→→
→ Programs →
→→
→ Xilinx ISE Design Suite 10.1i →
→→
→ EDK →
→→
→
Xilinx Platform Studio
Select Open a recent project, Click OK and browse to C:\xup\embedded\labs\lab3
Click system.xmp to open the project
Generate a Peripheral Template Step 2
You will use the Create/Import Peripheral Wizard to create a PLB bus
peripheral template.
In XPS, select Hardware → Create or Import Peripheral to start the wizard
Click Next to continue to the Create and Import Peripheral Wizard flow selection (Figure
3-2).
Figure 3-2. Create and Import User Peripheral Dialog Box
Adding Custom IP Lab: www.xilinx.com/univ 3-4
MicroBlaze Processor xup@xilinx.com
In the Select Flow panel, select Create templates for a new peripheral and click Next
Click next with the default option To an XPS project selected.
Figure 3-3. Repository or Project Dialog Box
Click Next and enter lcd_ip in the Name field, leave the default version number of 1.00.a,
click Next (see Figure 3-4)
Figure 3-4. Provide Core Name and Version Number
Select Processor Local Bus (PB v4.6), and click Next
Select option to store
peripheral in XPS project
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