【最新版可复制文字】JEDEC-JESD301-2-2022PMIC5100POWERMANAGEMEN

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JEDEC

STANDARD

PMIC5100 Power Management IC Standard

JESD301-2

Rev. 1.03

October 2022

JEDEC SOLID STATE TECHNOLOGY ASSOCIATION

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JEDEC

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JEDEC

JEDEC Standard No. 301-2

-i-

PMIC5100 POWER MANAGEMENT IC STANDARD

Contents

Pages

1 Scope.......................................................................................................................................................... 1

1.1 Device Standard ............................................................................................................................... 1

1.1.1 Description.............................................................................................................................. 1

1.1.2 Common Feature Summary.................................................................................................... 2

2 PMIC Pin List and Package....................................................................................................................... 3

2.1 Pin List ............................................................................................................................................. 3

2.2 Package ............................................................................................................................................ 4

2.2.1 Flip Chip QFN Package (3 mm x 4 mm)................................................................................ 4

2.2.2 Mechanical Drawing............................................................................................................... 4

2.2.3 Pinout (FC QFN Package - 28 Pins)....................................................................................... 7

3 Electrical Characteristics ........................................................................................................................... 9

3.1 Input Supply Electrical Characteristics............................................................................................ 9

3.2 Switch Regulator Output Electrical Characteristics....................................................................... 10

3.3 LDO Output Regulator Characteristics.......................................................................................... 11

3.4 I2C or I3C Basic DC and AC Electrical Characteristics................................................................ 12

3.5 Measurement Condition................................................................................................................. 16

3.6 PMIC AC Timing Parameters........................................................................................................ 17

3.7 Absolute Maximum Ratings .......................................................................................................... 18

3.8 ESD Requirements......................................................................................................................... 18

3.9 Thermal Characteristics ................................................................................................................. 19

4 Performance Characteristics .................................................................................................................... 20

4.1 Efficiency ....................................................................................................................................... 20

4.1.1 Efficiency with Inductor Footprint ....................................................................................... 20

4.2 Inductor Specification .................................................................................................................... 20

4.2.1 Mechanical Specification ..................................................................................................... 20

4.2.2 Electrical Specification......................................................................................................... 22

5 DDR5 DIMM Schematic......................................................................................................................... 23

6 Functional Operation ............................................................................................................................... 28

6.1 PMIC Input Voltage Supply and Ramp Condition ........................................................................ 28

6.2 Power Up Initialization Sequence.................................................................................................. 28

6.2.1 Power Up Sequence.............................................................................................................. 29

6.3 PMIC Output Rail Turn On Timing............................................................................................... 34

6.4 Secure Mode and Programmable Mode of Operation.................................................................... 35

6.5 Power Down Output Regulators .................................................................................................... 36

6.5.1 Programmable Mode Operation; R1A[4] = ‘0’ .................................................................... 36

6.5.2 Programmable Mode Operation; R1A[4] = ‘1’ .................................................................... 38

6.5.3 Secure Mode Operation; R1A[4] = ‘0’................................................................................. 41

6.5.4 Secure Mode Operation; R1A[4] = ‘1’................................................................................. 42

6.6 PMIC Output Rail Off Timing....................................................................................................... 46

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