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AS3992

UHF RFID Single Chip Reader EPC Class1 Gen2 Compatible

www.austriamicrosystems.com/AS3992 Revision 1.0 1 - 52

Data Sheet

1 General Description

The AS3992 UHF Gen2 Reader chip is an integrated analog front-

end and provides protocol handling for ISO180006c/b 900MHz RFID

reader systems. Equipped with multiple built-in programming

options, the device is suitable for a wide range of UHF RFID

applications.

The AS3992 is pin to pin and firmware compatible with the previous

AS3990/91 IC's. It offers improved receive sensitivity to -86dB,

programmable Rx Dense Reader Mode (DRM) filters on chip and

pre-distortion. Fully scalable, the AS3992 is ideal for longer range

and higher power applications.

Offering DRM filtering on chip, combined with improved sensitivity

and pre-distortion allows the AS3992 to be the only true world wide

shippable IC. The reader configuration is achieved through setting

control registers allowing fine tuning of different reader parameters.

Parallel or serial interface can be selected for communication

between the host system (MCU) and the reader IC. When hardware

coders and decoders are used for transmission and reception, data

is transferred via 24 bytes FIFO register. In case of direct

transmission or reception, coders and decoders are bypassed and

the host system can service the analog front end in real time.

The transmitter generates 20dBm output power into 50Ω load and is

capable of ASK or PR-ASK modulation. The integrated supply

voltage regulators ensure supply rejection of the complete reader

system.

The transmission system comprises low level data coding. Automatic

generation of FrameSync, Preamble, and CRC is supported.

The receiver system allows AM and PM demodulation. The receiver

also comprises automatic gain control option (patent pending) and

selectable gain and signal bandwidth to cover a range of input link

frequency and bit rate options. The signal strength of AM and PM

modulation is measured and can be accessed in RSSI register. The

receiver output is selectable between digitized sub-carrier signal and

any of integrated sub-carrier decoders. Selected decoders deliver bit

stream and data clock as outputs.

The receiver system also comprises framing system. This system

performs the CRC check and organizes the data in bytes. Framed

data is accessible to the host system through a 24 byte FIFO

To support external MCU and other circuitry a 3.3V regulated supply

and clock outputs are available. The regulated supply has 20mA

current capability.

The AS3992 is available in a 64-pin QFN (9mm x 9mm), ensuring

the smallest possible footprint.

2 Key Features

 ISO18000-6C (EPC Gen2) full protocol support

 ISO18000-6A,B compatibility in direct mode

 Programmable Dense Reader Mode filters on chip allowing a

true World Wide Shippable device.

 Improved receive sensitivity to -86dBm

 On chip pre-distortion meaning improved external PA efficiency

 Integrated low level transmission coding, Integrated low level

decoders

 Integrated data framing, Integrated CRC checking

 Parallel 8-bit or serial 4-pin SPI interface to MCU using 24 bytes

FIFO

 Voltage range for communication to MCU between 1.8V and

5.5V

 Can be powered by USB with no need for step conversion from

4.1 to 5.5 Volt.

 Selectable clock output for MCU

 Integrated supply voltage regulator (20mA), which can be used

to supply MCU and other external circuitry

 Integrated supply voltage regulator for the RF output stage,

providing rejection to supply noise

 Internal power amplifier (20dBm) for short range applications

 Modulator using ASK or PR-ASK modulation

 Adjustable ASK modulation index

 AM & PM demodulation ensuring no “communication holes”

with automatic I/Q selection

 Selectable reception gain, Reception automatic gain control

 AD converter for measuring TX power using external RF power

detector

 DA converter for controlling external power amplifier

 Frequency hopping support

 On-board VCO and PLL covering complete RFID frequency

range 840MHz to 960MHz

 Oscillator using 20MHz crystal

 Power down, standby and active mode available

3 Applications

The device is an ideal solution for UHF RFID reader systems and

hand-held UHF RFID readers.

www.austriamicrosystems.com/AS3992 Revision 1.0 3 - 52

AS3992

Data Sheet - Contents

Contents

1 General Description.................................................................................................................................................................. 1

2 Key Features............................................................................................................................................................................. 1

3 Applications............................................................................................................................................................................... 1

4 Pin Assignments....................................................................................................................................................................... 5

4.1 Pin Descriptions.................................................................................................................................................................................... 5

5 Absolute Maximum Ratings...................................................................................................................................................... 8

6 Electrical Characteristics........................................................................................................................................................... 9

7 Detailed Description................................................................................................................................................................ 11

7.1 Supply................................................................................................................................................................................................. 11

7.1.1 Power Modes............................................................................................................................................................................. 12

7.2 Host Communication .......................................................................................................................................................................... 12

7.3 VCO and PLL ..................................................................................................................................................................................... 13

7.3.1 VCO and External RF Source.................................................................................................................................................... 13

7.3.2 PLL ............................................................................................................................................................................................ 13

7.4 Chip Status Control ............................................................................................................................................................................ 13

7.5 Protocol Control.................................................................................................................................................................................. 13

7.6 Option Registers Preset ..................................................................................................................................................................... 14

7.7 Transmitter.......................................................................................................................................................................................... 14

7.7.1 Normal Mode ............................................................................................................................................................................. 14

7.7.2 Direct Mode ............................................................................................................................................................................... 15

7.7.3 Modulator................................................................................................................................................................................... 16

7.7.4 Amplifier..................................................................................................................................................................................... 16

7.7.5 TX Pre-Distortion ....................................................................................................................................................................... 17

7.8 Receiver ............................................................................................................................................................................................. 17

7.8.1 Input Mixer................................................................................................................................................................................. 17

7.8.2 DRM RX Filter............................................................................................................................................................................ 17

7.8.3 RX Filter Calibration................................................................................................................................................................... 18

7.8.4 Fast AC Coupling....................................................................................................................................................................... 18

7.8.5 RX Gain ..................................................................................................................................................................................... 19

7.8.6 Received Signal Strength Indicator (RSSI)................................................................................................................................ 19

7.8.7 Reflected RF Level Indicator ..................................................................................................................................................... 19

7.8.8 Normal Mode ............................................................................................................................................................................. 19

7.8.9 Direct Mode ............................................................................................................................................................................... 20

7.8.10 Normal Mode With Mixer DC Level Output and Enable RX Output Available......................................................................... 21

7.9 ADC / DAC ......................................................................................................................................................................................... 21

7.9.1 DA Converter............................................................................................................................................................................. 21

7.9.2 AD Converter............................................................................................................................................................................. 21

7.10 Reference Oscillator......................................................................................................................................................................... 21

8 Application Information ........................................................................................................................................................... 22

8.1 Configuration Registers Address Space............................................................................................................................................. 22

8.2 Main Configuration Registers ............................................................................................................................................................. 24

8.3 Control Registers - Low Level Configuration Registers...................................................................................................................... 25

8.4 Status Registers ................................................................................................................................................................................. 29

8.5 Test Registers..................................................................................................................................................................................... 32

8.6 PLL, Modulator, DAC, and ADC Registers......................................................................................................................................... 34

www.austriamicrosystems.com/AS3992 Revision 1.0 4 - 52

AS3992

Data Sheet - Contents

8.7 RX Length Registers .......................................................................................................................................................................... 37

8.8 FIFO Control Registers....................................................................................................................................................................... 38

8.9 Direct Commands............................................................................................................................................................................... 39

8.9.1 Idle (80)...................................................................................................................................................................................... 40

8.9.2 Hop to Main Frequency (84)...................................................................................................................................................... 40

8.9.3 Hop to Auxiliary Frequency (85) ................................................................................................................................................ 40

8.9.4 Trigger AD Conversion (87)....................................................................................................................................................... 40

8.9.5 Trigger RX Filter Calibration (88)............................................................................................................................................... 40

8.9.6 Decrease RX Filter Calibration Data (89) .................................................................................................................................. 40

8.9.7 Increase RX Filter Calibration Data (8A) ................................................................................................................................... 40

8.9.8 Reset FIFO (8F)......................................................................................................................................................................... 40

8.9.9 Transmission With CRC (90)..................................................................................................................................................... 40

8.9.10 Transmission With CRC Expecting Header Bit (91) ................................................................................................................ 41

8.9.11 Transmission Without CRC (92).............................................................................................................................................. 41

8.9.12 Delayed Transmission With CRC (93)..................................................................................................................................... 41

8.9.13 Delayed Transmission Without CRC (94)................................................................................................................................ 41

8.9.14 Block RX (96)........................................................................................................................................................................... 41

8.9.15 Enable RX (97) ........................................................................................................................................................................ 41

8.10 EPC GEN2 Specific Commands ...................................................................................................................................................... 41

8.10.1 Query (98)................................................................................................................................................................................ 41

8.10.2 QueryRep (99)......................................................................................................................................................................... 41

8.10.3 QueryAdjustUp (9A)................................................................................................................................................................. 41

8.10.4 QueryAdjustNic (9B)................................................................................................................................................................ 41

8.10.5 QueryAdjustDown (9C)............................................................................................................................................................ 42

8.10.6 ACK (9D) ................................................................................................................................................................................. 42

8.10.7 NAK (9E).................................................................................................................................................................................. 42

8.10.8 ReqRN (9F) ............................................................................................................................................................................. 42

8.11 Reader Communication Interface..................................................................................................................................................... 42

8.12 Parallel Interface Communication..................................................................................................................................................... 44

8.13 Serial Interface Communication ....................................................................................................................................................... 46

8.13.1 Timing Diagrams...................................................................................................................................................................... 47

8.13.2 Timing Parameters .................................................................................................................................................................. 48

8.14 FIFO ................................................................................................................................................................................................. 48

9 Package Drawings and Markings ........................................................................................................................................... 49

10 Ordering Information............................................................................................................................................................. 51