海思平台下IT6801驱动

///***************************************** // Copyright (C) 2009-2014 // ITE Tech. Inc. All Rights Reserved // Proprietary and Confidential ///***************************************** // @file <it680x.c> // @author Max.Kao@ite.com.tw // @date 2013/11/14 // @fileversion: ITE_IT6802_SAMPLE_V1.04 //******************************************/ //FIX_ID_001 //Dr. Liu suggestion to enable Auto EQ with Manual EQ to avoid some special HDMI cable issue. //FIX_ID_002 //Check IT6802 chip version Identify for TogglePolarity and Port 1 Deskew //FIX_ID_003 //Add IT6802 Video Output Configure setting //FIX_ID_004 //Add 100ms calibration for Cbus //FIX_ID_005 //Add Cbus Event Handler //FIX_ID_006 //Add P2_0 for switch Exteranl 24c04 EEPROM and Internal IT6802 EDID RAM //FIX_ID_007 //for debug IT6681 HDCP issue //FIX_ID_008 //Add SW reset when HDMI / MHL device un-plug !!! //FIX_ID_009 //Verify interrupt event with reg51[0] select port //FIX_ID_010 //Add JudgeBestEQ to avoid wrong EQ setting //FIX_ID_011 //Use FW send PATH_EN{Sink}=1 //FIX_ID_012 //For SamSung Galaxy Note wake up fail issue //FIX_ID_013 //For MSC 3D request issue //FIX_ID_014 //For HDCP Auth Start with EQ Adjust issue //FIX_ID_015 //Add RCP timeout mechanism for peer device no RCPK or RCPE response /*****************************************************************************/ /* Header Files Included *****************************************************/ /*****************************************************************************/ #define _MCU_ //#define EnableAdjustEQ #ifndef _IT680x_ #define _IT680x_ #endif #define _CODE const #include "Mhlrx.h" #include "Mhlrx_reg.h" #include "i2c_master.h" #include "msp430x22x4.h" //org ==> //#include "msp430f2132.h" #include "dpp343x.h" /*****************************************************************************/ /* Local Defines **********************************************************/ /*****************************************************************************/ //#define DISABLE_HDMI_CSC #define Enable_Vendor_Specific_packet //#define EN_DUAL_PIXEL_MODE //2013-0520 //FIX_ID_003 xxxxx //Add IT6802 Video Output Configure setting // 0 eRGB444_SDR=0, // 1 eYUV444_SDR, // 2 eRGB444_DDR, // 3 eYUV444_DDR, // 4 eYUV422_Emb_Sync_SDR, // 5 eYUV422_Emb_Sync_DDR, // 6 eYUV422_Sep_Sync_SDR, // 7 eYUV422_Sep_Sync_DDR, // 8 eCCIR656_Emb_Sync_SDR, // 9 eCCIR656_Emb_Sync_DDR, // 10 eCCIR656_Sep_Sync_SDR, // 11 eCCIR656_Sep_Sync_DDR, // 12 eRGB444_Half_Bus, // 13 eYUV444_Half_Bus, // 14 eBTA1004_SDR, // 15 eBTA1004_DDR //06-27 disable --> #define HDMIRX_OUTPUT_VID_MODE (F_MODE_EN_UDFILT | F_MODE_RGB444) #define HDMIRX_OUTPUT_VID_MODE eRGB444_SDR //FIX_ID_003 xxxxx #define MS_TimeOut(x) (x+1) #define VSATE_CONFIRM_SCDT_COUNT MS_TimeOut(2000) #define AUDIO_READY_TIMEOUT MS_TimeOut(20) #define AUDIO_MONITOR_TIMEOUT MS_TimeOut(150) #define SCDT_OFF_TIMEOUT MS_TimeOut(20) //100 x MS_LOOP = 5000 ms = 5 sec #define ECC_TIMEOUT MS_TimeOut(20) #define DESKEW_TIMEOUT MS_TimeOut(20) #ifdef Enable_OSC_8MHz #define WAKEUP_PULSE_TIMEOUT (1000/MS_LOOP) #define WAKEUP_FAIL_TIMEOUT (4000/MS_LOOP) #else #define WAKEUP_PULSE_TIMEOUT (600/MS_LOOP) #define WAKEUP_FAIL_TIMEOUT (2000/MS_LOOP) #endif // Debug Mode #define EnCBusDbgMode FALSE #define MSCCBusDbgCtrl TRUE #define DDCCBusDbgCtrl FALSE #define RCLKFreqSel 1 //; //0: RING/2 ; 1: RING/4 ; 2: RING/8 ; 3: RING/16 #define GenPktRecType 0x81 #define PPHDCPOpt TRUE //2013-0509 MHL 1080p packet pixel mode HDCP #ifndef IT6811B0 #define PPHDCPOpt2 TRUE //2013-0509 MHL 1080p packet pixel mode HDCP #else #define PPHDCPOpt2 FALSE //only for it6811b0 #endif //FIX_ID_004 xxxxx //Add 100ms calibration for Cbus #ifdef _SelectExtCrystalForCbus_ #define T10usSrcSel TRUE //FALSE: 100ms calibration , TRUR: 27MHz Crystal(only IT6802) #else #define T10usSrcSel FALSE //FALSE: 100ms calibration , TRUR: 27MHz Crystal(only IT6802) #endif //FIX_ID_004 xxxxx #define EnMSCBurstWr TRUE #define MSCBurstWrID TRUE // TRUE: from MHL5E/MHL5F #define MSCBurstWrOpt FALSE // TRUE: Not write Adopter ID unsigned char o ScratchPad #define EnPktFIFOBurst TRUE // DDC Option #define EnDDCSendAbort TRUE // Send ABORT after segment write with EOF //CBUS Capability #define MHLVersion 0x20 #define PLIM 1 #define POW 1 #define DEV_TYPE_SINK 1 //06-26 #define DEV_TYPE 1 #define ADOPTER_ID_H 0x02 #define ADOPTER_ID_L 0x45 #define DEVICE_ID_H 0x68 #define DEVICE_ID_L 0x02 #define AckHigh 0xB #define AckLow 1 // CBUS INput Option #define EnCBusDeGlitch TRUE //---------------------// //----- WatchDog -----// //--------------------// #define DeltaNum 1 #define RegBurstWrTOSel 2 // 2 //0: 320ms, 1: 340ms, 2: 360ms (ATC) #define Reg100msTOAdj 2 // 2 //00: 100ms, 01: 99ms, 10: 101ms (ATC) #define EnMSCHwRty FALSE #define EnHWPathEn FALSE #define MSCRxUCP2Nack TRUE ///////////////////////////////////////// //Cbus command fire wait time //Maxmun time for determin CBUS fail // CBUSWAITTIME(ms) x CBUSWAITNUM ///////////////////////////////////////// #define CBUSWAITTIME 10 #define CBUSWAITNUM 10 //#define IT6802_CHIP 1 //#define IT6801_CHIP 0 #define HDCPIntKey FALSE //TRUE: Internal HDCP Key, FALSE: SIPROM #define VCLK_INV 0 #define VCLK_DLY 0 #define EnMultiSeg TRUE #define EnIntEDID TRUE //Discovery #define CBUSFloatAdj FALSE #define EQFAILCNT 2 //FIX_ID_001 xxxxx Add Auto EQ with Manual EQ #define EQRETRYFAILCNT 1 // for EQ interrupt #define RCLKVALUE 12 // for show TMDS and Pixel Clk #define TMDSCLKVALUE 160 // for TMDS > 160 then set RS to 00, otherwise set to 3F #define TMDSCLKVALUE_1080P 160 // for TMDS > 160 then set RS to 00, otherwise set to 3F #define TMDSCLKVALUE_480P 35 #define TMDSCLKVALUE_MHL_ER1 90 #define JUDGE_ER1_VALUE 90 //FIX_ID_001 xxxxx //FIX_ID_004 xxxxx //Add 100ms calibration for Cbus #ifndef _SelectExtCrystalForCbus_ #define _RCLK_FREQ_20M FALSE #endif //FIX_ID_004 xxxxx //FIX_ID_005 xxxx //Wait for video on then read MHL device capability #define MAX_CBUS_WAITNO (250/MS_LOOP) // 250ms #define MAX_PATHEN_WAITNO (700/MS_LOOP) // 700ms #define MAX_BUSY_WAITNO (150/MS_LOOP) // 150ms #define MAX_DISCOVERY_WAITNO (100/MS_LOOP) // 100ms //FIX_ID_005 xxxx //FIX_ID_014 xxxx #define MAX_TMDS_WAITNO (350/MS_LOOP) // 400ms #define MAX_HDCP_WAITNO (100/MS_LOOP) // 150ms //FIX_ID_014 xxxx #define DEFAULT_EQVALUE 0x1F /*****************************************************************************/ /* Private and Local Variables ********************************************/ /*****************************************************************************/ #if 1 struct it6802_dev_data it6802DEV; unsigned char V3D_EntryCnt = 0; unsigned char wrburstoff, wrburstnum; unsigned char TxWrBstSeq = 0; //FIX_ID_013 xxxxx //For Acer MHL Dongle MSC 3D request issue //unsigned char EnMSCWrBurst3D = TRUE; //unsigned char EnMHL3DSupport = FALSE; //FIX_ID_013 xxxxx unsigned char p1deskewfailcnt = 0; unsigned char p1eccerrcnt = 0; unsigned char ucEqRetryCnt[2]; unsigned char wakeupfailcnt = 0; //FIX_ID_001 xxxxx Add Auto EQ with Manual EQ #ifdef _SUPPORT_EQ_ADJUST_ #define MaxEQIndex 3 unsigned char IT6802EQTable[]={0xFF,0x9F,0x83}; #define MINECCFAILCOUNT 6 //for EQ state machine handler //#define MAXSYNCOFF 5 #define MAXECCWAIT 10 #define EQSTATE_WAIT 10 #define EQSTATE_START 20 //(EQSTATE_WAIT+MAXECCWAIT) #define EQSTATE_LOW 30 //(EQSTATE_WAIT+EQSTATE_START+(MAXECCWAIT*1)) #define EQSTATE_MIDDLE 40 //(EQSTATE_WAIT+EQSTATE_START+(MAXECCWAIT*2)) #define EQSTATE_HIGH 50 //(EQST