Section number Title Page
Chapter 7
System Debug
7.1 Overview.......................................................................................................................................................................357
7.2 Chip and ARM Platform Debug Architecture.............................................................................................................. 357
7.2.1 Debug Features.......................................................................................................................................... 358
7.2.2 Debug system components.........................................................................................................................359
7.2.2.1 AMBA Trace Bus (ATB).......................................................................................................360
7.2.2.2 ATB replicator....................................................................................................................... 360
7.2.2.3 Embedded Cross Triggering.................................................................................................. 360
7.2.2.3.1 Cross-Trigger Matrix (CTM)..........................................................................361
7.2.2.3.2 Cross-Trigger Interface (CTI).........................................................................362
7.2.2.4 Debug Access Port (DAP)..................................................................................................... 362
7.2.3 Chip-Specific SJC Features....................................................................................................................... 363
7.2.3.1 JTAG Disable Mode.............................................................................................................. 363
7.2.3.2 JTAG ID.................................................................................................................................363
7.2.4 System JTAG Controller - SJC..................................................................................................................364
7.2.5 System JTAG controller main features......................................................................................................364
7.2.6 SJC TAP Port.............................................................................................................................................364
7.2.7 SJC main blocks.........................................................................................................................................365
7.3 Smart DMA (SDMA) core............................................................................................................................................365
7.3.1 SDMA On Chip Emulation Module (OnCE) Feature Summary............................................................... 366
7.3.1.1 Other SDMA Debug Functionality........................................................................................366
7.3.1.2 SDMA ROM Patching...........................................................................................................367
7.4 Miscellaneous............................................................................................................................................................... 367
7.4.1 Clock/Reset/Power.....................................................................................................................................367
7.5 Supported tools............................................................................................................................................................. 368
Chapter 8
System Boot
8.1 Overview.......................................................................................................................................................................369
i.MX 6Solo/6DualLite Applications Processor Reference Manual, Rev. 3, 09/2017
NXP Semiconductors 5