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### RC663数据手册详解：高性能NFC阅读器解决方案 #### 一、引言在探讨RC663的数据手册之前，我们首先简要了解RC663本身。RC663是恩智浦（NXP）半导体公司推出的一款高度集成的无接触式读写器集成电路（IC），专为13.56MHz的无接触通信设计。它不仅适用于传统的RFID（射频识别）应用，而且支持近场通信（NFC）标准，使其成为移动支付、门禁控制、身份验证等场景下的理想选择。 #### 二、功能与规格概述 RC663芯片具备以下关键特性和操作模式： 1. **读写模式**：支持ISO/IEC 14443A/MIFARE、ISO/IEC 14443B、JIS X6319-4（类似于FeliCa）、ISO/IEC 15693、ICODE EPC UIDs/EPC OTP以及ISO/IEC 18000-3 Mode 3/EPC Class-1 HF标准。 - ISO/IEC 14443A/MIFARE：广泛应用于交通卡、门禁卡等，支持MIFARE Classic 1K、4K、Ultralight、Ultralight C、PLUS和DESFire产品，双向传输速率最高可达848 kbit/s。 - ISO/IEC 14443B：用于高速数据传输，但抗碰撞功能需在主机控制器的固件及上层实现。 - FeliCa：源于日本的无接触智能卡标准，双向传输速率可达424 kbit/s，由RC663进行信号解调和错误检测（如CRC校验）。 2. **被动启动模式（Passive Initiator Mode）**：根据ISO/IEC 18092标准，允许设备在无需外部电源的情况下被唤醒并进行通信。 3. **内部发射器**：能够驱动设计用于与ISO/IEC 14443A/MIFARE卡片和应答器通信的读写器天线，无需额外的有源电路。数字模块管理完整的ISO/IEC 14443A帧构建和错误检测功能，包括奇偶校验和循环冗余校验（CRC）。 #### 三、RC663的应用优势 RC663的高性能和高集成度使其在多个方面展现出显著优势： 1. **兼容性广泛**：支持多种国际标准和协议，确保了其在不同应用场景中的通用性和互操作性。 2. **高效能数据传输**：高达848 kbit/s的双向传输速率，显著提升了数据交换速度，减少了等待时间，增强了用户体验。 3. **简化系统设计**：内部发射器和数字模块的集成，大大简化了硬件设计复杂度，降低了系统成本和功耗。 4. **被动启动能力**：支持被动启动模式，扩展了设备的应用范围，尤其适用于低功耗和移动设备。 #### 四、结论 RC663作为一款高性能的无接触读写器解决方案，通过其卓越的兼容性、高效的传输性能和简化的设计方案，在NFC和RFID领域占据了一席之地。无论是对于终端用户还是系统集成商而言，RC663都提供了一个强大而灵活的平台，满足了现代无接触通信技术的多样化需求。随着NFC和RFID技术的不断发展，RC663无疑将在未来的市场中发挥更加重要的作用。 --- RC663数据手册详细介绍了这款高性能NFC阅读器解决方案的技术规格、功能特性及其在无接触通信领域的广泛应用前景。对于从事相关行业或研究的人来说，深入理解RC663的特性和优势，将有助于更好地利用其潜力，推动技术进步和创新。

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1. Introduction

This document describes the functionality and electrical specifications of the contactless

reader/writer IC CLRC663.

2. General description

The CLRC663 is a highly integrated transceiver IC for contactless communication at

13.56 MHz.

The CLRC663 transceiver IC supports the following operating modes

• Read/write mode supporting ISO/IEC 14443A/MIFARE

• Read/write mode supporting ISO/IEC 14443B

• Read/write mode supporting JIS X 6319-4 (comparable with FeliCa

(see

Section 21.5

) scheme)

• Passive initiator mode according to ISO/IEC 18092

• Read/write mode supporting ISO/IEC 15693

• Read/write mode supporting ICODE EPC UID/ EPC OTP

• Read/write mode supporting ISO/IEC 18000-3 mode 3/ EPC Class-1 HF

The CLRC663’s internal transmitter is able to drive a reader/writer antenna designed to

communicate with ISO/IEC 14443A/MIFARE cards and transponders without additional

active circuitry. The digital module manages the complete ISO/IEC 14443A framing and

error detection functionality (parity and CRC).

The CLRC663 supports MIFARE Classic 1K, MIFARE Classic 4K, MIFARE Ultralight,

MIFARE Ultralight C, MIFARE PLUS and MIFARE DESFire products. The CLRC663

supports MIFARE higher transfer speeds of up to 848 kbit/s in both directions.

The CLRC663 supports layer 2 and 3 of the ISO/IEC 14443B reader/writer

communication scheme except anticollision. The anticollision needs to be implemented in

the firmware of the host controller as well as in the upper layers.

The CLRC663 is able to demodulate and decode FeliCa coded signals.The FeliCa

receiver part provides the demodulation and decoding circuitry for FeliCa coded signals.

The CLRC663 handles the FeliCa framing and error detection such as CRC. The

CLRC663 supports FeliCa higher transfer speeds of up to 424 kbit/s in both directions.

CLRC663

High performance NFC reader solution

Rev. 3.6 — 10 September 2013

171136

Product data sheet

COMPANY PUBLIC

1. In the following the word FeliCa is used for JIS X 6319-4

Product data sheet

COMPANY PUBLIC

Rev. 3.6 — 10 September 2013

171136 2 of 137

NXP Semiconductors

CLRC663

High performance NFC reader solution

The CLRC663 is supporting the P2P passive initiator mode in accordance with

ISO/IEC 18092.

The CLRC663 supports the vicinity protocol according to ISO/IEC15693, EPC UID and

ISO/IEC 18000-3 mode 3/ EPC Class-1 HF.

The following host interfaces are supported:

• Serial Peripheral Interface (SPI)

• Serial UART (similar to RS232 with voltage levels dependent on pin voltage supply)

• I

C-bus interface (two versions are implemented: I2C and I2CL)

The CLRC663 supports the connection of a secure access module (SAM). A dedicated

separate I2C interface is implemented for a connection of the SAM. The SAM can be used

for high secure key storage and acts as a very performant crypto coprocessor. A

dedicated SAM is available for connection to the CLRC663.

3. Features and benefits

 High RF output power frontend IC for transfer speed up to 848 kbit/s

 Supports ISO/IEC 14443 A/MIFARE, ISO/IEC 14443 B and FeliCa

 P2P passive initiator mode in accordance with ISO/IEC 18092

 Supports ISO/IEC15693, ICODE EPC UID and ISO/IEC 18000-3 mode 3/ EPC

Class-1 HF

 Supports MIFARE Classic encryption in read/write mode

 Low-Power Card Detection

 Compliance to “EMV contactless protocol specification V2.0.1” on RF level can be

achieved

 Antenna connection with minimum number of external components

 Supported host interfaces:

 SPI up to 10 Mbit/s

 I

C-bus interfaces up to 400 kBd in Fast mode, up to 1000 kBd in Fast mode plus

 RS232 Serial UART up to 1228.8 kBd, with voltage levels dependent on pin

voltage supply

 Separate I

C-bus interface for connection of a secure access module (SAM)

 FIFO buffer with size of 512 byte for highest transaction performance

 Flexible and efficient power saving modes including hard power down, standby and

low-power card detection

 Cost saving by integrated PLL to derive system CPU clock from 27.12 MHz RF quartz

crystal

 3 V to 5.5 V power supply

 Up to 8 free programmable input/output pins

 Typical operating distance in read/write mode for communication to a

ISO/IEC 14443A/MIFARE Card up to 12 cm, depending on the antenna size and

tuning

Product data sheet

COMPANY PUBLIC

Rev. 3.6 — 10 September 2013

171136 5 of 137

NXP Semiconductors

CLRC663

High performance NFC reader solution

7.1 Pin description

[1] This pin is used for connection of a buffer capacitor. Connection of a supply voltage might damage the device.

Table 3. Pin description

Pin Symbol Type Description

1 TDO O test data output for boundary scan interface

2 TDI I test data input boundary scan interface

3 TMS I test mode select boundary scan interface

4 TCK I test clock boundary scan interface

5 SIGIN I Contactless communication interface output.

6 SIGOUT O Contactless communication interface input.

7 DVDD PWR digital power supply buffer

[1]

8 VDD PWR power supply

9 AVDD PWR analog power supply buffer

[1]

10 AUX1 O auxiliary outputs: Pin is used for analog test signal

11 AUX2 O auxiliary outputs: Pin is used for analog test signal

12 RXP I receiver input pin for the received RF signal.

13 RXN I receiver input pin for the received RF signal.

14 VMID PWR internal receiver reference voltage

[1]

15 TX2 O transmitter 2: delivers the modulated 13.56 MHz carrier

16 TVSS PWR transmitter ground, supplies the output stage of TX1, TX2

17 TX1 O transmitter 1: delivers the modulated 13.56 MHz carrier

18 TVDD PWR transmitter voltage supply

19 XTAL1 I crystal oscillator input: Input to the inverting amplifier of the oscillator. This is pin is also the

input for an externally generated clock (fosc = 27,12 MHz)

20 XTAL2 O crystal oscillator output: output of the inverting amplifier of the oscillator

21 PDOWN I Power Down

22 CLKOUT O clock output

23 SCL O Serial Clock line

24 SDA I/O Serial Data Line

25 PVDD PWR pad power supply

26 IFSEL0 I host interface selection 0

27 IFSEL1 I host interface selection 1

28 IF0 I/O interface pin, multifunction pin: Can be assigned to host interface RS232, SPI, I

C, I

C-L

29 IF1 I/O interface pin, multifunction pin: Can be assigned to host interface SPI, I

C, I

C-L

30 IF2 I/O interface pin, multifunction pin: Can be assigned to host interface RS232, SPI, I

C, I

C-L

31 IF3 I/O interface pin, multifunction pin: Can be assigned to host interface RS232, SPI, I

C, I

C-L

32 IRQ O interrupt request: output to signal an interrupt event

33 VSS PWR ground and heatsink connection

剩余136页未读，继续阅读

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2015-11-20

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