djtag_tap_top_no_fsm

jtag tap控制器。非状态机实现。 The JTAG TAP controller used for development purposes (Boundary Scan testing, Memory BIST and debugging) and is as such an interface between the processor(s), peripheral cores, and any commercial debugger/emulator or BS testing device. The external debugger or BS tester connects to the core via a fully IEEE 1149.1 compatible JTAG port. This core connects to the debug interface that is interface to the cores that are being debugged (see “dbg_interface” on Opencores web page).