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Verilog Hardware Description
Language Reference Manual
(LRM)
Version 1.0
November, 1991
Open Verilog International
Copyright
©
1991 by Open Verilog International, Inc. All rights reserved.
No part of this work covered by the copyright hereon may be reproduced or used in any form or by any means --
- graphic, electronic, or mechanical, including photocopying, recording, taping, or information storage and
retrieval systems --- without the prior written approval of Open Verilog International.
Additional copies of this manual may be purchased by contacting Open Verilog International at the address
shown below.
Notices
The information contained in this draft manual represents the definition of the Verilog hardware description lan-
guage as it existed at the time Cadence Design Systems, Inc. transferred the language and its documentation to
Open Verilog International (OVI). This manual does not contain any language changes or additions developed or
approved by OVI. This information constitutes the basis from which OVI may make refinements and/or addi-
tions to the language.
Open Verilog International makes no warranties whatsoever with respect to the completeness, accuracy, or appli-
cability of the information in this draft manual to a user’s requirements.
Open Verilog International reserves the right to make changes to the Verilog hardware description language and
this manual at any time without notice.
Open Verilog International does not endorse any particular simulator or other CAE tools that is based on the Ver-
ilog hardware description language.
Suggestions for improvements to the Verilog hardware description language and/or to this manual will be wel-
come. They should be sent to the address below.
Information about Open Verilog International and membership enrollment can be obtained by inquiring at the
address below.
Published as: Verilog Hardware Description Language Reference Manual, Release 1.0, November, 1991.
Printed in the United States of America.
Published by: Open Verilog International
Suite 408
1016 East El Camino Real
Sunnyvale, CA 94087
Verilog
®
is a registered trademark of Cadence Design Systems, Inc.
Version 1.0 Contents-1
Table of Contents
1 Introduction ____________________________________________________ 1-1
1.1 Criteria for Selecting Material for This Manual ________________________ 1-3
1.2 The Contents of the Reference Manual _______________________________ 1-3
2 Lexical Conventions ______________________________________________ 2-1
2.1 Operators ______________________________________________________ 2-1
2.2 White Space and Comments _______________________________________ 2-2
2.3 Numbers ______________________________________________________ 2-2
2.4 Strings ________________________________________________________ 2-5
2.4.1 String Variable Declaration ______________________________________ 2-5
2.4.2 String Manipulation ____________________________________________ 2-6
2.4.3 Special Characters in Strings _____________________________________ 2-7
2.5 Identifiers, Keywords, and System Names ____________________________ 2-7
2.5.1 Escaped Identifiers _____________________________________________ 2-8
2.5.2 Keywords ____________________________________________________ 2-9
2.5.3 The $keyword Construct _______________________________________ 2-9
2.5.4 The `keyword Construct _______________________________________ 2-10
2.6 Text Substitutions _______________________________________________ 2-10
3 Data Types _____________________________________________________ 3-1
3.1 Value Set ______________________________________________________ 3-1
3.2 Registers and Nets _______________________________________________ 3-2
3.2.1 Nets _________________________________________________________ 3-2
3.2.2 Registers _____________________________________________________ 3-2
3.2.3 Declaration Syntax _____________________________________________ 3-3
3.2.4 Declaration Examples __________________________________________ 3-4
3.3 Vectors ________________________________________________________ 3-5
3.3.1 Specifying Vectors _____________________________________________ 3-5
3.3.2 Vector Net Accessibility ________________________________________ 3-6
3.4 Strengths ______________________________________________________ 3-6
3.4.1 Charge Strength _______________________________________________ 3-6
3.4.2 Drive Strength ________________________________________________ 3-7
3.5 Implicit Declarations _____________________________________________ 3-7
3.6 Net Initialization ________________________________________________ 3-7
3.7 Net Types _____________________________________________________ 3-8
3.7.1 wire and tri Nets _______________________________________________ 3-8
3.7.2 Wired Nets ___________________________________________________ 3-8
3.7.3 trireg Net ____________________________________________________ 3-9
3.7.4 tri0 and tri1 Nets _______________________________________________ 3-13
3.7.5 supply Nets ___________________________________________________ 3-13
3.8 Memories ______________________________________________________ 3-14
3.9 Integers and Times ______________________________________________ 3-16
3.10 Real Numbers __________________________________________________ 3-17
3.10.1 Declaration Syntax for Real Numbers ______________________________ 3-17
3.10.2 Specifying Real Numbers ________________________________________ 3-18
3.10.3 Operators and Real Numbers _____________________________________ 3-18
Contents-2
Version 1.0
3.10.4 Conversion ____________________________________________________ 3-19
3.11 Parameters _____________________________________________________ 3-19
4 Expressions _____________________________________________________ 4-1
4.1 Operators ______________________________________________________ 4-2
4.1.1 Binary Operator Precedence ______________________________________ 4-4
4.1.2 Numeric Conventions in Expressions _______________________________ 4-5
4.1.3 Arithmetic Operators ____________________________________________ 4-5
4.1.4 Arithmetic Expressions with Registers and Integers ____________________ 4-6
4.1.5 Relational Operators ____________________________________________ 4-7
4.1.6 Equality Operators ______________________________________________ 4-8
4.1.7 Logical Operators ______________________________________________ 4-8
4.1.8 Bit-Wise Operators _____________________________________________ 4-10
4.1.9 Reduction Operators ____________________________________________ 4-11
4.1.10 Syntax Restrictions _____________________________________________ 4-12
4.1.11 Shift Operators _________________________________________________ 4-13
4.1.12 Conditional Operator ____________________________________________ 4-14
4.1.13 Concatenations ________________________________________________ 4-15
4.2 Operands ______________________________________________________ 4-15
4.2.1 Net and Register Bit Addressing ___________________________________ 4-16
4.2.2 Memory Addressing ____________________________________________ 4-17
4.2.3 Strings _______________________________________________________ 4-18
4.2.4 String Operations _______________________________________________ 4-19
4.2.5 String Value Padding and Potential Problems _________________________ 4-19
4.2.6 Null String Handling ____________________________________________ 4-20
4.3 Minimum, Typical, Maximum Delay Expressions ______________________ 4-20
4.4 Expression Bit Lengths ___________________________________________ 4-21
4.4.1 An Example of an Expression Bit Length Problem ____________________ 4-22
4.4.2 Verilog Rules for Expression Bit Lengths ____________________________ 4-22
5 Assignments ____________________________________________________ 5-1
5.1 Continuous Assignments _________________________________________ 5-2
5.1.1 The Net Declaration Assignment __________________________________ 5-3
5.1.2 The Continuous Assignment Statement _____________________________ 5-3
5.1.3 Delays _______________________________________________________ 5-5
5.1.4 Strength ______________________________________________________ 5-6
5.2 Procedural Assignments ___________________________________________ 5-7
6 Gate and Switch Level Modeling ___________________________________ 6-1
6.1 Gate and Switch Declaration Syntax _________________________________ 6-1
6.2 and, nand, nor, or, xor, and xnor Gates __________________________ 6-5
6.3 buf and not Gates ______________________________________________ 6-7
6.4 bufif1, bufif0, notif1, and notif0 Gates ______________________ 6-8
6.5 MOS Switches __________________________________________________ 6-9
6.6 Bidirectional Pass Switches ________________________________________ 6-11
6.7 cmos Gates ____________________________________________________ 6-12
6.8 pullup and pulldown Sources __________________________________ 6-13
Version 1.0 Contents-3
6.9 Implicit Net Declarations _________________________________________ 6-14
6.10 Logic Strength Modeling __________________________________________ 6-14
6.11 Strengths and Values of Combined Signals ___________________________ 6-16
6.11.1 Combined Signals of Unambiguous Strength ________________________ 6-16
6.11.2 Ambiguous Strengths: Sources and Combinations ____________________ 6-18
6.11.3 Ambiguous Strength Signals and Unambiguous Signals ________________ 6-24
6.11.4 Wired Logic Net Types _________________________________________ 6-28
6.12 Strength Reduction by Non-Resistive Devices _________________________ 6-31
6.13 Strength Reduction by Resistive Devices _____________________________ 6-31
6.14 Strengths of Net Types ___________________________________________ 6-31
6.14.1 tri0 and tri1 Net Strengths ___________________________________ 6-32
6.14.2 trireg Strength ______________________________________________ 6-32
6.14.3 supply0 and supply1 Net Strengths ____________________________ 6-32
6.15 Gate and Net Delays _____________________________________________ 6-32
6.15.1 min/typ/max Delays ____________________________________________ 6-35
6.15.2 trireg Net Charge Decay ______________________________________ 6-36
7 User-Defined Primitives (UDPs) ____________________________________ 7-1
7.1 Syntax ________________________________________________________ 7-3
7.2 UDP Definition _________________________________________________ 7-4
7.2.1 UDP Terminals ________________________________________________ 7-5
7.2.2 UDP Declarations ______________________________________________ 7-5
7.2.3 Sequential UDP initial Statement ______________________________ 7-5
7.2.4 UDP State Table _______________________________________________ 7-5
7.3 Combinational UDPs _____________________________________________ 7-6
7.4 Level-Sensitive Sequential UDPs ___________________________________ 7-8
7.5 Edge-Sensitive UDPs ____________________________________________ 7-9
7.6 Sequential UDP Initialization ______________________________________ 7-10
7.7 UDP Instances __________________________________________________ 7-13
7.8 Symbols to Enhance Readability ____________________________________ 7-14
7.9 Mixing Level and Edge-Sensitive Descriptions ________________________ 7-15
7.10 Reducing Pessimism _____________________________________________ 7-17
7.11 Level-Sensitive Dominance _______________________________________ 7-19
7.12 Summary of Symbols ____________________________________________ 7-19
7.13 Examples ______________________________________________________ 7-21
8 Behavioral Modeling _____________________________________________ 8-1
8.1 Behavioral Model Overview _______________________________________ 8-1
8.2 Procedural Assignments __________________________________________ 8-3
8.2.1 Blocking Procedural Assignments _________________________________ 8-4
8.2.2 The Non-Blocking Procedural Assignment __________________________ 8-4
8.2.3 How the Simulator Processes Blocking and _________________________
Non-Blocking Procedural Assignments ________________ 8-11
8.3 Conditional Statement ____________________________________________ 8-11
8.3.1 if-else-if Construct ________________________________________ 8-14
8.3.2 Example _____________________________________________________ 8-14
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