Anew6-bit250MS/sanalog-to-digitalconverter资源-CSDN文库

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A new 6-bit 250 MS/s analog-to-digital converter (ADC) is proposed for low-power low-cost CMOS integrated systems. This design is based on an improved successive approximation ADC with a mixed-mode subtracter that minimizes the overall power consumption and system complexity. The experimental results indicate that this ADC works up to 250 MS/s with power consumption less than 30 mW at 3.3 V. Moreover, the operating voltage is scaled down to 0.8 V using a slight adjustment. The ADC occupies only 0.1 mm2 with the TSMC 0.35- m single ploy quadruple metal (SPQM) CMOS technology. This design is suitable for standard CMOS technology with low-power low-cost VLSI implementation. ### 一种新型6位250 MS/s模拟到数字转换器的设计与实现 #### 概述本篇文章介绍了一种新型6位250 MS/s模拟到数字转换器（Analog-to-Digital Converter, ADC）的设计，该设计适用于低功耗、低成本的互补金属氧化物半导体（Complementary Metal-Oxide-Semiconductor, CMOS）集成系统。文章详细讨论了该ADC的设计原理、技术特点以及实验结果，并对其在低电压操作下的性能进行了评估。 #### 设计原理及技术特点 ##### 成功逼近型ADC架构该ADC基于改进的成功逼近型ADC架构。成功逼近型ADC是一种常见的高速转换器，通过逐步逼近输入信号值来完成模数转换过程。本设计中的ADC采用了一种混合模式减法器（mixed-mode subtracter），该减法器能够在保持高转换速度的同时，显著降低整体功耗和系统复杂度。 ##### 混合模式减法器混合模式减法器是该ADC的核心部分之一，它通过优化电路设计来减少功耗并简化系统结构。这种减法器结合了模拟和数字两种操作方式，在保证转换精度的同时降低了能量消耗。 ##### 低功耗与低成本该ADC的设计目标是在保证高性能的前提下实现低功耗和低成本。通过优化电路结构和使用先进的制造工艺，使得该ADC能够在3.3 V电压下工作时的功率消耗低于30 mW，而且可以通过微调进一步将工作电压降至0.8 V，这对于电池供电的便携式设备尤其重要。 #### 实验结果与性能评估实验结果显示，该ADC能够达到250 MS/s的采样速率，且在3.3 V电压下的功耗低于30 mW。此外，通过调整可以将工作电压降至0.8 V，这表明该ADC具有良好的电压适应性。整个转换器的尺寸仅为0.1 mm²，采用台积电0.35 μm单层多晶硅四层金属（Single Poly Quadruple Metal, SPQM）CMOS技术制造。这样的设计非常适合于标准CMOS技术下的低功耗、低成本超大规模集成电路（Very Large Scale Integration, VLSI）实现。 #### 应用场景与未来展望由于其出色的性能指标，特别是低功耗和小尺寸特性，该ADC非常适合应用于对功耗敏感的便携式电子设备中，如移动电话、便携式媒体播放器等。同时，由于采用了标准的CMOS技术，该ADC还非常适合嵌入到系统级芯片（System-on-Chip, SoC）电路设计中，为现代电子产品的集成化提供了有力的支持。 #### 结论本文介绍了一种基于改进成功逼近型ADC架构的新型6位250 MS/s模拟到数字转换器。该ADC通过采用混合模式减法器实现了低功耗、低成本的目标，并且在实验中展示了良好的性能。此外，该ADC还具备较低的工作电压范围，使其成为便携式电子设备的理想选择。未来，随着制造工艺的进步和技术的发展，这种类型的ADC有望在更多领域得到广泛应用。

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54 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 1, JANUARY 2003

A New Successive Approximation Architecture for

Low-Power Low-Cost CMOS A/D Converter

Chi-Sheng Lin and Bin-Da Liu, Senior Member, IEEE

Abstract—A new 6-bit 250 MS/s analog-to-digital converter

(ADC) is proposed for low-power low-cost CMOS integrated

systems. This design is based on an improved successive ap-

proximation ADC with a mixed-mode subtracter that minimizes

the overall power consumption and system complexity. The

experimental results indicate that this ADC works up to 250 MS/s

with power consumption less than 30 mW at 3.3 V. Moreover, the

operating voltage is scaled down to 0.8 V using a slight adjustment.

The ADC occupies only 0.1 mm

with the TSMC 0.35- m single

ploy quadruple metal (SPQM) CMOS technology. This design is

suitable for standard CMOS technology with low-power low-cost

VLSI implementation. It is well applied when embedded into

system-on-chip (SoC) circuit designs.

Index Terms—ADC, low voltage, parallel-like, successive

approximation.

I. INTRODUCTION

IGH performance CMOS analog-to-digital converters

(ADCs) are key components in mixed-signal integrated

circuits. Recent ADC applications are used increasingly in

digital data reading fields, such as hard disk drives, digital

videodiscs and local-area networks [1], [2]. High sampling

speed is required in all of these applications, resolution as low

as 6-bit, however, is sufficient.

Among these low-resolution high-speed CMOS ADC design

techniques, the flash architecture is one of the best solutions

for high-speed low-latency operations [3]. However, with the

number of bits

, the flash architecture requires com-

parators and the power, area and input capacitance are propor-

tional to

. Folding CMOS ADC is another good architec-

ture for high-speed operations and simple hardware design. This

is a technique for reducing the number of comparators used in

the flash architecture [4]. However, their performance degrades

with process variation [3].

In portable system designs, a low-voltage operation plays one

of the key design factors. The voltage limitations of this tech-

nology dictate that the ADC operates at the same low voltage

as the digital circuitry. In the literature, many low-voltage

CMOS ADC integrated circuits have been proposed [5], [6].

However, most of them are more complex circuit designs or

require higher power consumption. Consequently, they are not

suitable for portable system designs.

Manuscript received April 3, 2002; revised August 5, 2002. This work was

supported in part by the Chip Implementation Center, National Science Council

and by the Program of Promoting Academic Excellence, Ministry of Education,

under Grant EX-91-E-FA09-5-4, Taiwan, R.O.C.

The authors are with the Department of Electrical Engineering, Na-

tional Cheng Kung University, Tainan 70101, Taiwan, R.O.C. (e-mail:

bdliu@cad.ee.ncku.edu.tw).

Digital Object Identifier 10.1109/JSSC.2002.806257

Fig. 1. Circuit diagram of a general successive approximation ADC.

In this paper, a novel circuit for low-power low-cost 6-bit

CMOS ADC is presented. A basic successive approximation

ADC (SA-ADC) will first be introduced and followed by an im-

proved successive approximation ADC (ISA-ADC) with stan-

dard CMOS technology. Based on the ISA-ADC architecture, a

parallel-like ISA-ADC architecture for high-speed low-resolu-

tion applications is developed.In addition, the adjustable feature

of the proposed circuit for scaling down the operating voltage

will be shown. The proposed converter has a simple hardware

design and low-accuracy comparator and therefore, is suitable

for low-power low-cost standard CMOS technology VLSI im-

plementation.

II. B

ASIC ARCHITECTURES OF SUCCESSIVE

APPROXIMATION ADC

The architecture of a general SA-ADC usually consists of

a rail-to-rail analog comparator, a digital-to-analog converter

(DAC)andasuccessiveapproximationregister (SAR), as shown

in Fig. 1 [7]. In general, the SAR is designed into the digital

circuitry. The DAC required in the ADC is designed based on

a R-2R ladder. Thus, both of them are suitable for the stan-

dard CMOS technology VLSI implementation. However, real-

izing a high-speed, high-accuracy and rail-to-rail MOS com-

parator concurrently remains a problem because of MOS device

mismatches [8], [9] and threshold voltage limitations [10]. The

input signals of this comparator is expressed by

(1)

where both

and are the comparator inputs and denotes

the comparator operation. This high-speed, offset compensated

and rail-to-rail comparator plays one of the key components for

SA-ADC designs.

To solve this problem, another SA-ADC architecture was de-

veloped to simplify the comparator requirement, as shown in

Fig. 2 [11]. This architecture employs an additional analog sub-

tracter to generate the differential value between the

signal

and the

signal, this way a comparator based on this archi-

tecture is applicable to compare the differential voltage level

LIN AND LIU: APPROXIMATION ARCHITECTURE FOR LOW-POWER LOW-COST CMOS A/D CONVERTER 55

Fig. 2. Circuit diagram of a successive approximation ADC with fixed voltage

comparator.

( ) with the fixed voltage level (ground signal). The

input signals of this comparator is expressed by

(2)

However, some problems exist in the analog subtracter design

because the analog subtracter requires capacitors [11] or dual

supply voltage [12] to implement the subtracting function in the

analog domain. This is not recommended in SOC solutions. If

the ADC is implemented in standard CMOS and single supply

voltage technology, then both the manufacturing cost and the

integrated effort are reduced.

III. T

HE ISA-ADC CIRCUIT DESIGN

To solve these SA-ADC challenges implemented with the

standard CMOS technology, a ISA-ADC architecture with

simple comparison skill is proposed. The reference voltage

(

), at full-scale analog value for the input signal is defined.

Using (2), since the

signal is generated by the digital code

as shown in Fig. 2, the expression is written as shown in (3) at

Fig. 3. Circuit diagram of the improvedsuccessive approximation (ISA) ADC.

the bottom of the page. where is the output digital code for

the ADC and

Fig. 3 shows the circuit diagram of the ISA-ADC. In the tra-

ditional SA-ADCs shown in Fig. 1, the comparator design plays

a crucial role in the overall system performance [9]. More ad-

vances in MOS designs allow MOS comparators to be realized

for higher-speed applications. However, it is difficult to achieve

high-speed, high-accuracy and rail-to-rail concurrently, because

of MOS device mismatches and threshold voltage limitations.

In the ISA-ADC design, from (3), the comparator is applied

to compare a differential voltage level

with

a fixed voltage level

. Therefore, in the

ISA-ADC architecture, the comparator circuit design focus on

low-power,low-cost, and high-speed issues without considering

the rail-to-rail problem. Fig. 4 shows the circuit diagram for the

low-cost, low-power, high-speed comparator [12].

The minimization of circuit capacitances and having

one of the inputs fixed near half the reference voltage

result in achieving the high-speed com-

parator operation. However, the accuracy of this comparator

does not meet the requirements, because of the minimized

MOS device and process variations. In the ideal comparator

design with single supply voltage

, shorting the inputs

ofa comparator together should yield

. However,

as a result of inherent mismatches between the input stages,

a practical comparator will generally yield

(3)

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