51单片机I2C汇编总线程序资源-CSDN文库

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i2c.rar （25个子文件）

i2c

I2C.ASM 2KB

I2C.BIN 24B

I2C.PWI 1KB

i2c.uvproj 13KB

MAIN.LST 10KB

I2C.OBJ 2KB

i2c.plg 5KB

Last Loaded SPI.DBK 97KB

MAIN.INC 236B

24aa256.pdf 1.2MB

i2c.hex 691B

I2C.INC 453B

i2c.uvopt 6KB

i2c.lnp 51B

MAIN.OBJ 2KB

i2c.uvgui.eng7 71KB

i2c.LST 14KB

I2C.TXT 164B

I2C.DSN 134KB

test.LST 3KB

Last Loaded I2C.DBK 134KB

MAIN.ASM 1KB

i2c.M51 13KB

i2c.uvgui_eng7.bak 70KB

i2c 3KB

 1998-2013 Microchip Technology Inc. DS20001203U-page 1

24AA256/24LC256/24FC256

Device Selection Table

Features:

• Single Supply with Operation Down to 1.7V for

24AA256 and 24FC256 Devices, 2.5V for

24LC256 Devices

• Low-Power CMOS Technology:

- Read current: 400 uA max. at 5.5V, 400 kHz

- Standby current: 1 uA max. at 3.6V, I-temp

• 2-Wire Serial Interface, I

™

Compatible

• Cascadable up to Eight Devices

• Schmitt Trigger Inputs for Noise Suppression

• Output Slope Control to Eliminate Ground Bounce

• 100 kHz and 400 kHz Clock Compatibility

• Page Write Time 5 ms Max.

• Self-Timed Erase/Write Cycle

• 64-Byte Page Write Buffer

• Hardware Write-Protect

• ESD Protection >4000V

• More than One Million Erase/Write Cycles

• Data Retention >200 years

• Factory Programming Available

• Packages Include 8-lead PDIP, SOIC, SOIJ, DFN,

TDFN, TSSOP and MSOP

• RoHS Compliant

• Temperature Ranges:

Description:

The Microchip Technology Inc. 24AA256/24LC256/

24FC256 (24XX256*) is a 32K x 8 (256 Kbit) Serial

Electrically Erasable PROM, capable of operation

across a broad voltage range (1.7V to 5.5V). It has

been developed for advanced, low-power applications

such as personal communications or data acquisition.

This device also has a page write capability of up to 64

bytes of data. This device is capable of both random

and sequential reads up to the 256K boundary.

Functional address lines allow up to eight devices on

the same bus, for up to 2 Mbit address space. This

device is available in the standard 8-pin plastic DIP,

SOIC, SOIJ, TSSOP, MSOP, DFN and TDFN pack-

ages. The 24AA256 is also available in the 8-lead Chip

Scale package.

Block Diagram

Package Types

*24XX256 is used in this document as a generic part number for the 24AA256/24LC256/24FC256 devices.

Part

Number

VCC

Range

Max. Clock

Frequency

Temp.

Ranges

24AA256 1.7-5.5V 400 kHz

(1)

I, E

24LC256 2.5-5.5V 400 kHz I, E

24FC256 1.7-5.5V 1 MHz

(2)

Note 1: 100 kHz for V

CC < 2.5V.

2: 400 kHz for V

CC < 2.5V.

- Industrial (I): -40C to +85C

- Automotive (E): -40C to +125C

HV Generator

EEPROM

Array

Page Latches

YDEC

XDEC

Sense Amp.

R/W Control

Memory

Control

Logic

I/O

Control

Logic

I/O

A0 A1A2

SDA

SCL

VSS

VCC

SCL

SDA

24XX256

PDIP/SOIC/SOIJ

TSSOP/MSOP

(1)

SCL

SDA

24XX256

DFN/TDFN

SCL

SDA

24XX256

VCC

Note 1: * Pins A0 and A1 are no connects for the MSOP package only.

Note 2: Available in I-temp, “AA” only.

CS (Chip Scale)

(2)

CC A1 A0

WP A2

SDA SCL V

(TOP DOWN VIEW,

BALLS NOT VISIBLE)

256K I

C™ CMOS Serial EEPROM

24AA256/24LC256/24FC256

DS20001203U-page 2  1998-2013 Microchip Technology Inc.

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. V

SS ......................................................................................................... -0.6V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-40°C to +125°C

ESD protection on all pins  4kV

TABLE 1-1: DC CHARACTERISTICS

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at these or any other conditions above those

indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

DC CHARACTERISTICS

Electrical Characteristics:

Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C

Automotive (E): V

CC = +1.7V to 5.5V TA = -40°C to +125°C

Param.

No.

Sym. Characteristic Min. Max. Units Conditions

— A0, A1, A2, SCL, SDA

and WP pins:

————

D1 V

IH High-level input voltage 0.7 VCC —V—

D2 VIL Low-level input voltage — 0.3 VCC

0.2 VCC

VCC  2.5V

CC < 2.5V

D3 V

HYS Hysteresis of Schmitt

Trigger inputs

(SDA, SCL pins)

0.05 V

CC —VVCC  2.5V (Note)

D4 VOL Low-level output voltage — 0.40 V IOL = 3.0 mA @ VCC = 4.5V

OL = 2.1 mA @ VCC = 2.5V

D5 ILI Input leakage current — ±1 AVIN = VSS or VCC, WP = VSS

VIN = VSS or VCC, WP = VCC

D6 ILO Output leakage current — ±1 AVOUT = VSS or VCC

D7 CIN,

OUT

Pin capacitance

(all inputs/outputs)

—10pFVCC = 5.0V (Note)

A = 25°C, FCLK = 1 MHz

D8 ICC Read Operating current — 400 AVCC = 5.5V, SCL = 400 kHz

ICC Write — 3 mA VCC = 5.5V

D9 I

CCS Standby current — 1.5 ATA = -40°C to +85°C

SCL = SDA = V

CC = 5.5V

A0, A1, A2, WP = V

—1ATA = -40°C to +85°C

SCL = SDA = V

CC = 3.6V

A0, A1, A2, WP = V

—5ATA = -40°C to +125°C

SCL = SDA = V

CC = 5.5V

A0, A1, A2, WP = V

Note: This parameter is periodically sampled and not 100% tested.

 1998-2013 Microchip Technology Inc. DS20001203U-page 3

24AA256/24LC256/24FC256

TABLE 1-2: AC CHARACTERISTICS

AC CHARACTERISTICS

Electrical Characteristics:

Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C

Automotive (E): V

CC = +1.7V to 5.5V TA = -40°C to +125°C

Param.

No.

Sym. Characteristic Min. Max. Units Conditions

CLK Clock frequency —

—

100

400

1000

kHz 1.7V  VCC  2.5V

2.5V  V

CC  5.5V

1.7V  V

CC  2.5V 24FC256

2.5V  V

CC  5.5V 24FC256

2THIGH Clock high time 4000

600

500

—

ns 1.7V  VCC  2.5V

2.5V  V

CC  5.5V

1.7V  V

CC  2.5V 24FC256

2.5V  V

CC  5.5V 24FC256

LOW Clock low time 4700

1300

500

—

ns 1.7V  VCC  2.5V

2.5V  V

CC  5.5V

1.7V  V

CC  2.5V 24FC256

2.5V  V

CC  5.5V 24FC256

4TR SDA and SCL rise time

(Note 1)

—

1000

300

ns 1.7V  VCC  2.5V

2.5V  V

CC  5.5V

1.7V  V

CC  5.5V 24FC256

5TF SDA and SCL fall time

(Note 1)

—

300

100

ns All except, 24FC256

1.7V  V

CC  5.5V 24FC256

HD:STA Start condition hold time 4000

600

250

—

ns 1.7V  VCC  2.5V

2.5V  V

CC  5.5V

1.7V  V

CC  2.5V 24FC256

2.5V  V

CC  5.5V 24FC256

7TSU:STA Start condition setup time 4700

600

250

—

ns 1.7V  VCC  2.5V

2.5V  V

CC  5.5V

1.7V  V

CC  2.5V 24FC256

2.5V  V

CC  5.5V 24FC256

8THD:DAT Data input hold time 0 — ns (Note 2)

SU:DAT Data input setup time 250

100

—

ns 1.7V  V

CC  2.5V

2.5V  V

CC  5.5V

1.7V  V

CC  5.5V 24FC256

10 T

SU:STO Stop condition setup time 4000

600

250

—

ns 1.7V  VCC  2.5V

2.5V  V

CC  5.5V

1.7V  V

CC  2.5V 24FC256

2.5V  V

CC  5.5V 24FC256

11 TSU:WP WP setup time 4000

600

—

ns 1.7V  VCC  2.5V

2.5V  V

CC  5.5V

1.7V  V

CC  5.5V 24FC256

12 THD:WP WP hold time 4700

1300

—

ns 1.7V  VCC  2.5V

2.5V  V

CC  5.5V

1.7V  V

CC  5.5V 24FC256

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combined T

SP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved

noise spike suppression. This eliminates the need for a T

I specification for standard operation.

4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site

at www.microchip.com.

24AA256/24LC256/24FC256

DS20001203U-page 4  1998-2013 Microchip Technology Inc.

FIGURE 1-1: BUS TIMING DATA

13 TAA Output valid from clock

(Note 2)

—

3500

900

400

ns 1.7 V  VCC  2.5V

2.5 V  V

CC  5.5V

1.7V  V

CC  2.5V 24FC256

2.5 V  V

CC  5.5V 24FC256

14 TBUF Bus free time: Time the bus

must be free before a new

transmission can start

4700

1300

500

—

ns 1.7V  VCC  2.5V

2.5V  V

CC  5.5V

1.7V  V

CC  2.5V 24FC256

2.5V  V

CC  5.5V 24FC256

15 T

OF Output fall time from VIH

minimum to VIL maximum

B  100 pF

10 + 0.1CB 250

250

ns All except, 24FC256 (Note 1)

16 T

SP Input filter spike suppression

(SDA and SCL pins)

— 50 ns All except, 24FC256 (Notes 1

and 3)

17 T

WC Write cycle time (byte or

page)

—5ms—

18 — Endurance 1,000,000 — cycles Page mode, 25°C, 5.5V (Note 4)

AC CHARACTERISTICS (Continued)

Electrical Characteristics:

Industrial (I): V

CC = +1.7V to 5.5V TA = -40°C to +85°C

Automotive (E): V

CC = +1.7V to 5.5V TA = -40°C to +125°C

Param.

No.

Sym. Characteristic Min. Max. Units Conditions

Note 1: Not 100% tested. C

B = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combined T

SP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved

noise spike suppression. This eliminates the need for a T

I specification for standard operation.

4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site

at www.microchip.com.

(unprotected)

(protected)

SCL

SDA

OUT

 1998-2013 Microchip Technology Inc. DS20001203U-page 5

24AA256/24LC256/24FC256

2.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Tab le 2- 1.

TABLE 2-1: PIN FUNCTION TABLE

2.1 A0, A1, A2 Chip Address Inputs

The A0, A1 and A2 inputs are used by the 24XX256 for

multiple device operations. The levels on these inputs

are compared with the corresponding bits in the slave

address. The chip is selected if the compare is true.

For the MSOP package only, pins A0 and A1 are not

connected.

Up to eight devices (two for the MSOP package) may

be connected to the same bus by using different Chip

Select bit combinations. These inputs must be

connected to either V

CC or VSS.

In most applications, the chip address inputs A0, A1

and A2 are hard-wired to logic ‘0’ or logic ‘1’. For

applications in which these pins are controlled by a

microcontroller or other programmable device, the chip

address pins must be driven to logic ‘0’ or logic ‘1’

before normal device operation can proceed.

2.2 Serial Data (SDA)

This is a bidirectional pin used to transfer addresses

and data into and out of the device. It is an open drain

terminal. Therefore, the SDA bus requires a pull-up

resistor to V

CC (typical 10 k for 100 kHz, 2 k for

400kHz and 1MHz).

For normal data transfer, SDA is allowed to change

only during SCL low. Changes during SCL high are

reserved for indicating the Start and Stop conditions.

2.3 Serial Clock (SCL)

This input is used to synchronize the data transfer to

and from the device.

2.4 Write-Protect (WP)

This pin must be connected to either VSS or VCC. If tied

to V

SS, write operations are enabled. If tied to VCC,

write operations are inhibited but read operations are

not affected.

3.0 FUNCTIONAL DESCRIPTION

The 24XX256 supports a bidirectional 2-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as a transmitter and a device

receiving data as a receiver. The bus must be

controlled by a master device which generates the

Serial Clock (SCL), controls the bus access, and

generates the Start and Stop conditions while the

24XX256 works as a slave. Both master and slave can

operate as a transmitter or receiver, but the master

device determines which mode is activated.

Name PDIP SOIC SOIJ TSSOP MSOP DFN TDFN CS Function

A0 1 1 1 1 — 1 1 3 User Configurable Chip Select

A1 2 2 2 2 — 2 2 2 User Configurable Chip Select

(NC) — — — — 1, 2 — — — Not Connected

A2 3 3 3 3 3 3 3 5 User Configurable Chip Select

SS 4 4 4 4 4 4 4 8 Ground

SDA 5 5 5 5 5 5 5 6 Serial Data

SCL6666 6667Serial Clock

WP 7 7 7 7 7 7 7 4 Write-Protect Input

CC 8 8 8 8 8 8 8 1 +1.7V to 5.5V (24AA256)

+2.5V to 5.5V (24LC256)

+1.7V to 5.5V (24FC256)

Note: Exposed pad on DFN/TDFN can be connected to V

SS or left floating.

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