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TMS320F2808
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TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SPRS230K
October 2003 – Revised June 2009
Contents
TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
SPRS230K – OCTOBER 2003 – REVISED JUNE 2009
www.ti.com
1 F280x, F2801x, C280x DSPs .................................................................................................. 9
1.1 Features ....................................................................................................................... 9
1.2 Getting Started .............................................................................................................. 10
2 Introduction ....................................................................................................................... 11
2.1 Pin Assignments ............................................................................................................ 13
2.2 Signal Descriptions ......................................................................................................... 19
3 Functional Overview ........................................................................................................... 25
3.1 Memory Maps ............................................................................................................... 26
3.2 Brief Descriptions ........................................................................................................... 34
3.2.1 C28x CPU ....................................................................................................... 34
3.2.2 Memory Bus (Harvard Bus Architecture) .................................................................... 34
3.2.3 Peripheral Bus .................................................................................................. 34
3.2.4 Real-Time JTAG and Analysis ................................................................................ 35
3.2.5 Flash .............................................................................................................. 35
3.2.6 ROM ............................................................................................................... 35
3.2.7 M0, M1 SARAMs ............................................................................................... 35
3.2.8 L0, L1, H0 SARAMs ............................................................................................ 36
3.2.9 Boot ROM ........................................................................................................ 36
3.2.10 Security .......................................................................................................... 37
3.2.11 Peripheral Interrupt Expansion (PIE) Block .................................................................. 38
3.2.12 External Interrupts (XINT1, XINT2, XNMI) ................................................................... 38
3.2.13 Oscillator and PLL .............................................................................................. 38
3.2.14 Watchdog ........................................................................................................ 38
3.2.15 Peripheral Clocking ............................................................................................. 38
3.2.16 Low-Power Modes .............................................................................................. 38
3.2.17 Peripheral Frames 0, 1, 2 (PFn) .............................................................................. 39
3.2.18 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 39
3.2.19 32-Bit CPU-Timers (0, 1, 2) ................................................................................... 39
3.2.20 Control Peripherals ............................................................................................. 39
3.2.21 Serial Port Peripherals ......................................................................................... 40
3.3 Register Map ................................................................................................................ 40
3.4 Device Emulation Registers ............................................................................................... 42
3.5 Interrupts .................................................................................................................... 42
3.5.1 External Interrupts .............................................................................................. 45
3.6 System Control ............................................................................................................. 46
3.6.1 OSC and PLL Block ............................................................................................ 47
3.6.1.1 External Reference Oscillator Clock Option ....................................................... 48
3.6.1.2 PLL-Based Clock Module ............................................................................ 49
3.6.1.3 Loss of Input Clock ................................................................................... 50
3.6.2 Watchdog Block ................................................................................................. 51
3.7 Low-Power Modes Block .................................................................................................. 52
4 Peripherals ........................................................................................................................ 53
4.1 32-Bit CPU-Timers 0/1/2 .................................................................................................. 53
4.2 Enhanced PWM Modules (ePWM1/2/3/4/5/6) .......................................................................... 55
4.3 Hi-Resolution PWM (HRPWM) ........................................................................................... 57
4.4 Enhanced CAP Modules (eCAP1/2/3/4) ................................................................................ 58
4.5 Enhanced QEP Modules (eQEP1/2) ..................................................................................... 60
4.6 Enhanced Analog-to-Digital Converter (ADC) Module ................................................................ 62
4.6.1 ADC Connections if the ADC Is Not Used ................................................................... 65
4.6.2 ADC Registers ................................................................................................... 66
Contents 2 Submit Documentation Feedback
TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
www.ti.com
SPRS230K – OCTOBER 2003 – REVISED JUNE 2009
4.7 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B) ..................................... 67
4.8 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B) .................................................... 72
4.9 Serial Peripheral Interface (SPI) Modules (SPI-A, SPI-B, SPI-C, SPI-D) ........................................... 75
4.10 Inter-Integrated Circuit (I2C) .............................................................................................. 79
4.11 GPIO MUX .................................................................................................................. 81
5 Device Support .................................................................................................................. 85
5.1 Device and Development Support Tool Nomenclature ................................................................ 85
5.2 Documentation Support ................................................................................................... 87
6 Electrical Specifications ...................................................................................................... 91
6.1 Absolute Maximum Ratings ............................................................................................... 91
6.2 Recommended Operating Conditions ................................................................................... 92
6.3 Electrical Characteristics ................................................................................................. 92
6.4 Current Consumption ..................................................................................................... 93
6.4.1 Reducing Current Consumption .............................................................................. 97
6.4.2 Current Consumption Graphs .................................................................................. 98
6.5 Emulator Connection Without Signal Buffering for the DSP ........................................................ 100
6.6 Timing Parameter Symbology ........................................................................................... 101
6.6.1 General Notes on Timing Parameters ....................................................................... 101
6.6.2 Test Load Circuit .............................................................................................. 102
6.6.3 Device Clock Table ........................................................................................... 102
6.7 Clock Requirements and Characteristics ............................................................................. 104
6.8 Power Sequencing ........................................................................................................ 105
6.8.1 Power Management and Supervisory Circuit Solutions ................................................... 105
6.9 General-Purpose Input/Output (GPIO) ................................................................................. 108
6.9.1 GPIO - Output Timing ......................................................................................... 108
6.9.2 GPIO - Input Timing ........................................................................................... 109
6.9.3 Sampling Window Width for Input Signals .................................................................. 110
6.9.4 Low-Power Mode Wakeup Timing ........................................................................... 111
6.10 Enhanced Control Peripherals .......................................................................................... 114
6.10.1 Enhanced Pulse Width Modulator (ePWM) Timing ........................................................ 114
6.10.2 Trip-Zone Input Timing ........................................................................................ 114
6.10.3 External Interrupt Timing ...................................................................................... 116
6.10.4 I2C Electrical Specification and Timing ..................................................................... 117
6.10.5 Serial Peripheral Interface (SPI) Master Mode Timing .................................................... 117
6.10.6 SPI Slave Mode Timing ....................................................................................... 121
6.10.7 On-Chip Analog-to-Digital Converter ........................................................................ 124
6.10.7.1 ADC Power-Up Control Bit Timing .............................................................. 125
6.10.7.2 Definitions ........................................................................................... 126
6.10.7.3 Sequential Sampling Mode (Single-Channel) (SMODE = 0) ................................. 127
6.10.7.4 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) ............................... 128
6.11 Detailed Descriptions .................................................................................................... 129
6.12 Flash Timing ............................................................................................................... 130
6.13 ROM Timing (C280x only) ............................................................................................... 131
7 Migrating From F280x Devices to C280x Devices .................................................................. 132
7.1 Migration Issues ........................................................................................................... 132
8 Revision History ............................................................................................................... 133
9 Mechanical Data ............................................................................................................... 135
Contents 3
TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
SPRS230K – OCTOBER 2003 – REVISED JUNE 2009
www.ti.com
List of Figures
2-1 TMS320F2809, TMS320F2808 100-Pin PZ LQFP (Top View) ............................................................. 14
2-2 TMS320F2806 100-Pin PZ LQFP (Top View) ................................................................................. 15
2-3 TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801 100-Pin PZ LQFP (Top View) ...................... 16
2-4 TMS320F2801x 100-Pin PZ LQFP (Top View) ............................................................................... 17
2-5 TMS320F2809, TMS320F2808, TMS320F2806,TMS320F2802, TMS320F2801,
TMS320F28016, TMS320F28015, TMS320C2802, TMS320C2801
100-Ball GGM and ZGM MicroStar BGA™ (Bottom View) .................................................................. 18
3-1 Functional Block Diagram ........................................................................................................ 25
3-2 F2809 Memory Map .............................................................................................................. 26
3-3 F2808 Memory Map .............................................................................................................. 27
3-4 F2806 Memory Map .............................................................................................................. 28
3-5 F2802, C2802 Memory Map ..................................................................................................... 29
3-6 F2801, F28015, F28016, C2801 Memory Map ............................................................................... 30
3-7 External and PIE Interrupt Sources ............................................................................................. 43
3-8 Multiplexing of Interrupts Using the PIE Block ................................................................................ 44
3-9 Clock and Reset Domains ....................................................................................................... 46
3-10 OSC and PLL Block Diagram ................................................................................................... 47
3-11 Using a 3.3-V External Oscillator ............................................................................................... 48
3-12 Using a 1.8-V External Oscillator ............................................................................................... 48
3-13 Using the Internal Oscillator ..................................................................................................... 48
3-14 Watchdog Module ................................................................................................................. 51
4-1 CPU-Timers ........................................................................................................................ 53
4-2 CPU-Timer Interrupt Signals and Output Signal .............................................................................. 54
4-3 Multiple PWM Modules in a 280x System ..................................................................................... 55
4-4 ePWM Sub-Modules Showing Critical Internal Signal Interconnections ................................................... 57
4-5 eCAP Functional Block Diagram ................................................................................................ 58
4-6 eQEP Functional Block Diagram ................................................................................................ 60
4-7 Block Diagram of the ADC Module ............................................................................................. 63
4-8 ADC Pin Connections With Internal Reference ............................................................................... 64
4-9 ADC Pin Connections With External Reference .............................................................................. 65
4-10 eCAN Block Diagram and Interface Circuit .................................................................................... 68
4-11 eCAN-A Memory Map ............................................................................................................ 69
4-12 eCAN-B Memory Map ............................................................................................................ 70
4-13 Serial Communications Interface (SCI) Module Block Diagram ............................................................ 74
4-14 SPI Module Block Diagram (Slave Mode) ..................................................................................... 78
4-15 I2C Peripheral Module Interfaces ............................................................................................... 80
4-16 GPIO MUX Block Diagram ....................................................................................................... 81
4-17 Qualification Using Sampling Window .......................................................................................... 84
5-1 Example of TMS320x280x/2801x Device Nomenclature .................................................................... 86
6-1 Typical Operational Current Versus Frequency (F2808) .................................................................... 98
List of Figures4 Submit Documentation Feedback
TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
www.ti.com
SPRS230K – OCTOBER 2003 – REVISED JUNE 2009
6-2 Typical Operational Power Versus Frequency (F2808) ...................................................................... 98
6-3 Typical Operational Current Versus Frequency (C280x) .................................................................... 99
6-4 Typical Operational Power Versus Frequency (C280x) ...................................................................... 99
6-5 Emulator Connection Without Signal Buffering for the DSP ............................................................... 100
6-6 3.3-V Test Load Circuit ......................................................................................................... 102
6-7 Clock Timing ..................................................................................................................... 105
6-8 Power-on Reset .................................................................................................................. 106
6-9 Warm Reset ...................................................................................................................... 107
6-10 Example of Effect of Writing Into PLLCR Register .......................................................................... 108
6-11 General-Purpose Output Timing ............................................................................................... 108
6-12 Sampling Mode .................................................................................................................. 109
6-13 General-Purpose Input Timing ................................................................................................. 110
6-14 IDLE Entry and Exit Timing .................................................................................................... 111
6-15 STANDBY Entry and Exit Timing Diagram ................................................................................... 112
6-16 HALT Wake-Up Using GPIOn ................................................................................................. 113
6-17 PWM Hi-Z Characteristics ...................................................................................................... 114
6-18 ADCSOCAO or ADCSOCBO Timing ......................................................................................... 116
6-19 External Interrupt Timing ....................................................................................................... 116
6-20 SPI Master Mode External Timing (Clock Phase = 0) ...................................................................... 119
6-21 SPI Master Mode External Timing (Clock Phase = 1) ...................................................................... 121
6-22 SPI Slave Mode External Timing (Clock Phase = 0) ........................................................................ 122
6-23 SPI Slave Mode External Timing (Clock Phase = 1) ........................................................................ 123
6-24 ADC Power-Up Control Bit Timing ............................................................................................ 125
6-25 ADC Analog Input Impedance Model ......................................................................................... 126
6-26 Sequential Sampling Mode (Single-Channel) Timing ....................................................................... 127
6-27 Simultaneous Sampling Mode Timing ........................................................................................ 128
List of Figures 5
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