verilog 串口，代码简洁，注释详细

FPGA 实现 RS-232 串口收发的仿真过程（Quartus+Synplify+ModelSim）(2007-

09-11 12:17:37)



网上关于 RS-232 的异步收发介绍得很多，最近没事学着摸索用 ModelSim 来做时序仿真，

就结合网上的参考资料和自己的琢磨，做了这个东西。

针对我这个小程序结合 FPGA 的开发流程，主要走了以下几步：

1. 文本程序输入（Verilog HDL）

2. 功能仿真（ModelSim，查看逻辑功能是否正确，要写一个 Test Bench）

0. 原理

略

一、文本程序输入（Verilog HDL）

发送端：

module trans(clk,

 rst,

 TxD_start,

 TxD_data,

 TxD,

 TxD_busy

 TxD_busy;

reg TxD;

reg [7:0] TxD_dataReg; // 寄存器发送模式，因为在串口发送过程中输入端不可能一直保持

有效电平

reg [3:0] state;

parameter ClkFrequency = 25000000; // 时钟频率－25 MHz

parameter Baud = 115200; // 串口波特率－115200

// 波特率产生

parameter BaudGeneratorAccWidth = 16;

reg [BaudGeneratorAccWidth:0] BaudGeneratorAcc;

 BaudGeneratorAcc <= 0;

else if(TxD_busy)

 BaudGeneratorAcc <= BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] + BaudGeneratorInc;

// 发送端状态

wire TxD_ready = (state==0); // 当 state = 0 时，处于准备空闲状态，TxD_ready = 1

assign TxD_busy = ~TxD_ready; // 空闲状态时 TxD_busy = 0

// 把待发送数据放入缓存寄存器 TxD_dataReg

always @(posedge clk or negedge rst)

 if(~rst)

 TxD_dataReg <= 8'b00000000;

 begin

 state <= 4'b0000; // 复位时，状态为 0000，发送端一直发 1 电平

 TxD <= 1'b1;

 end

else

case(state)

4'b0000: if(TxD_start) begin

 state <= 4'b0100; // 接受到发送信号，进入发送状态

  end

4'b0100: if(BaudTick) begin

 state <= 4'b1000; // 发送开始位 - 0 电平

 TxD <= 1'b0;

 end

 TxD <= TxD_dataReg[1];

 state <= 4'b1100; // bit 3

 TxD <= TxD_dataReg[3];

 end

4'b1100: if(BaudTick) begin

 state <= 4'b1101; // bit 4

 TxD <= TxD_dataReg[4];

4'b1101: if(BaudTick) begin

 state <= 4'b1110; // bit 5

 TxD <= TxD_dataReg[5];

 end

4'b1110: if(BaudTick) begin

 state <= 4'b1111; // bit 6

4'b0010: if(BaudTick) begin

 state <= 4'b0011; // stop1

 TxD <= 1'b1;

 end

4'b0011: if(BaudTick) begin

 state <= 4'b0000; // stop2

  TxD <= 1'b1;

 end

default: if(BaudTick) begin

 state <= 4'b0000;

 TxD <= 1'b1;

module rcv(clk,

 rst,

 RxD;

reg[2:0] bit_spacing;

reg  RxD_delay;

reg RxD_data_ready;

// 波特率产生，使用 8 倍过采样

parameter Baud8 = Baud*8;

parameter Baud8GeneratorAccWidth = 16;

wire  [Baud8GeneratorAccWidth:0] Baud8GeneratorInc =

((Baud8<<(Baud8GeneratorAccWidth-7))+(ClkFrequency>>8))/(ClkFrequency>>7);

reg [Baud8GeneratorAccWidth:0] Baud8GeneratorAcc;

always @(posedge clk or negedge rst)

 if(~rst)

 Baud8GeneratorAcc <= 0;

always @(posedge clk or negedge rst)

if(~rst||(state==0))

 bit_spacing <= 0;

// 检测到 RxD 有下跳沿时，RxD_start 置 1，准备接收数据

always@(posedge clk)

if(Baud8Tick)

begin

RxD_delay <= RxD;

 RxD_start <= (Baud8Tick & RxD_delay & (~RxD));

end

 state <= 4'b0000;

elseif(Baud8Tick)

 case(state)

 4'b1010: if(next_bit) state <= 4'b1011; // bit 2

 4'b1101: if(next_bit) state <= 4'b1110; // bit 5

 4'b1111: if(next_bit) state <= 4'b0001; // bit 7

 default: state <= 4'b0000;

 endcase

// 保存接收数据到 RxD_data 中

always @(posedge clk or negedge rst)

 if(~rst)

 RxD_data <= 8'b00000000;

else if(Baud8Tick && next_bit && state[3])

RxD_data <= {RxD, RxD_data[7:1]};

// RxD_data_ready 置位信号

always @(posedge clk or negedge rst)

 if(~rst)

 RxD_data_ready <= 0;