PC/104-Plus Specification Version — Page ii
Version 2.0, November, 2003
a. Chapter 1. Introduction and contact information updated
b. Chapter 2. PCI Signal Definition
1. All PCI signal names have been updated to reflect the PCI Specification Version 2.2
2. Signals SBO* and SDONE have been removed to reflect PCI Version 2.2
3. “(Not Supported)” has been placed under the Present signal in Figure 2
4. PCI signal descriptions in section 2.1 have been updated to reflect the PCI Specification Version 2.2
5. Section 2.2 has been updated with additional figures and descriptions to help clarify the purpose for signal
selection on the expansion modules. Figure 2 and Table 1 reflect the addition of a 4
th
GNT# and REQ# pair
to allow for a 4
th
bus mastering expansion module on a PC/104-Plus stack. The “ID Address” column has
been removed from table 1 since this is dependent on the PCI Host module.
c. Chapter 3. Electrical Specification
1. References to PCI specification Version 2.1 have been change to PCI Specification Version 2.2
2. Section 3.2.4 “Key Locations has been eliminated. Description for the identification of the PCI signaling
type has been moved to the “Mechanical Specification” chapter
3. Note 1 of Table 2 has been changed to reflect that the Host board does not need to supply 3.3V to the PCI
bus if it is using 3.3V PCI signaling. As with 5V PCI signaling Host cards, it is up to the user to supply
3.3V to the stack.
4. New section on PCI Signaling Voltage (VI/O) Requirements was added. This section discusses 3.3V, 5V,
and Universal Add-In Cards
d. Chapter 4. Levels of Conformance
1. PCI-104 section was removed since it will be covered in its own Specification Manual
e. Chapter 5. Mechanical Specifications
1. Section on clock trace lengths was added
2. A section has been added “Board Identifier” which describes how to label a board to indicate its PCI
signaling voltage level capabilities. This replaces the keying of the PCI connector.
f. Appendix A. Mechanical Dimensions
1. Figure 4 has been redone in AutoCAD showing both English and Metric units. The shroud keep out region
was also added. So was an area for connector overhang at the lower right hand side of the ISA bus.
2. Figure 5: Note 1 “DIN 41612 Part 5 “ has been removed since this does not apply to the PCI connector
3. Contact finish female interface changed from 20 micoinches minimum to 15 microinches in Figures 9 & 11
4. Mechanical performance withdrawal force changed from 1 ounce minimum average to 1 ounce per pin
minimum in Figures 9 & 11
g. Appendix B. Bus Signal Assignments
1. Pin B30 (Reserved) replaced with REQ3#
2. Pin C30 (Reserved) replaced with GNT3#
3. Pin C9 (SBO*) replaced with Reserved to reflect the PCI Local Bus Specification Revision 2.2
4. Pin D10 (SDONE) replaced with Reserved to reflect the PCI Local Bus Specification Revision 2.2
5. Note 2 at the bottom of Table 3 has been removed
h. Specification has been reformatted and updated
1. Chapter 2 “PCI Signal Definition” is now Chapter 3.
2. Chapter 3 “Electrical Specification” is now Chapter 4.
3. Chapter 4 “Levels of Conformance” is now Chapter 5.
4. Chapter 5 “Mechanical Specifications” is now Chapter 6.
5. Chapter 6 “Typical Stack” is now Chapter 2
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