################################################################################
# Vivado (TM) v2019.1 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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FPGA ARtix-7 ego1
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FPGA ARtix-7 ego1 (284个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
xsim.ini.bak 26KB
elaborate.bat 1KB
simulate.bat 894B
compile.bat 828B
runme.bat 229B
runme.bat 229B
runme.bat 229B
shumaguan.bit 2.09MB
xsim_1.c 17KB
xsim.dbg 16KB
shumaguan_routed.dcp 456KB
shumaguan_placed.dcp 389KB
shumaguan_opt.dcp 256KB
shumaguan.dcp 134KB
clk_wiz_0.dcp 9KB
clk_wiz_0.dcp 9KB
clk_wiz_0.dcp 9KB
compile.do 719B
compile.do 695B
compile.do 654B
compile.do 644B
simulate.do 311B
simulate.do 306B
simulate.do 306B
simulate.do 195B
elaborate.do 183B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
xsimk.exe 396KB
run.f 506B
run.f 490B
usage_statistics_webtalk.html 33KB
usage_statistics_ext_xsim.html 3KB
.xsim_webtallk.info 65B
xsim.ini 26KB
xsim.ini 25KB
xsimSettings.ini 1KB
webtalk.jou 955B
webtalk_4796.backup.jou 954B
vivado.jou 792B
vivado.jou 769B
vivado.jou 764B
ISEWrap.js 8KB
ISEWrap.js 8KB
ISEWrap.js 8KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
runme.log 31KB
runme.log 23KB
runme.log 23KB
webtalk_4796.backup.log 1KB
webtalk.log 1KB
xvlog.log 1KB
elaborate.log 1007B
xsimkernel.log 322B
simulate.log 50B
xsimcrash.log 0B
project_shumaguan99999.lpr 343B
xsim.mem 27KB
xsim_0.win64.obj 385KB
xsim_1.win64.obj 12KB
elab.opt 188B
vivado.pb 38KB
vivado.pb 36KB
place_design.pb 17KB
route_design.pb 14KB
opt_design.pb 11KB
init_design.pb 5KB
write_bitstream.pb 3KB
xelab.pb 2KB
xvlog.pb 2KB
shumaguan_power_summary_routed.pb 728B
shumaguan_utilization_placed.pb 242B
shumaguan_utilization_synth.pb 242B
clk_wiz_0_utilization_synth.pb 242B
vivado.pb 149B
shumaguan_timing_summary_routed.pb 109B
shumaguan_methodology_drc_routed.pb 52B
shumaguan_route_status.pb 44B
shumaguan_drc_routed.pb 37B
shumaguan_drc_opted.pb 37B
shumaguan_bus_skew_routed.pb 30B
shuma_vlog.prj 625B
vlog.prj 269B
xsim.reloc 16KB
xil_defaultlib.rlx 2KB
xsim.rlx 777B
shumaguan_timing_summary_routed.rpt 139KB
shumaguan_io_placed.rpt 97KB
shumaguan_clock_utilization_routed.rpt 16KB
shumaguan_utilization_placed.rpt 9KB
shumaguan_power_routed.rpt 8KB
shumaguan_utilization_synth.rpt 7KB
clk_wiz_0_utilization_synth.rpt 6KB
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