################################################################################
# Vivado (TM) v2018.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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FPGA实现的直方图均衡算法,包括源码,仿真文件,visio原理图
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FPGA实现的直方图均衡算法,包括源码,仿真文件,visio原理图 FPGA实现的直方图均衡算法,包括源码,仿真文件,visio原理图 FPGA实现的直方图均衡算法,包括源码,仿真文件,visio原理图 FPGA实现的直方图均衡算法,包括源码,仿真文件,visio原理图 FPGA实现的直方图均衡算法,包括源码,仿真文件,visio原理图 FPGA实现的直方图均衡算法,包括源码,仿真文件,visio原理图FPGA实现的直方图均衡算法,包括源码,仿真文件,visio原理图FPGA实现的直方图均衡算法,包括源码,仿真文件,visio原理图 FPGA实现的直方图均衡算法,包括源码,仿真文件,visio原理图 FPGA实现的直方图均衡算法,包括源码,仿真文件,visio原理图 FPGA实现的直方图均衡算法,包括源码,仿真文件,visio原理图
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FPGA实现的直方图均衡算法,包括源码,仿真文件,visio原理图 (243个子文件)
__synthesis_is_complete__ 0B
xsim.ini.bak 23KB
elaborate.bat 956B
compile.bat 850B
simulate.bat 822B
runme.bat 229B
test.bmp 376KB
xsim_1.c 10KB
xsim_1.c 8KB
xsim.dbg 105KB
xsim.dbg 74KB
blk_mem_gen_0.dcp 50KB
blk_mem_gen_0.dcp 50KB
blk_mem_gen_0.dcp 50KB
blk_mem_gen_0.dcp 41KB
blk_mem_gen_0.dcp 41KB
blk_mem_gen_0.dcp 34KB
compile.do 737B
compile.do 687B
compile.do 673B
simulate.do 341B
simulate.do 340B
simulate.do 340B
compile.do 310B
elaborate.do 213B
simulate.do 203B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
xsimk.exe 140KB
xsimk.exe 125KB
run.f 514B
run.f 494B
usage_statistics_ext_xsim.html 3KB
usage_statistics_ext_xsim.html 3KB
.xsim_webtallk.info 65B
.xsim_webtallk.info 64B
modelsim.ini 123KB
xsim.ini 23KB
xsim.ini 22KB
xsimSettings.ini 1KB
xsimSettings.ini 1KB
webtalk_23760.backup.jou 957B
webtalk.jou 957B
webtalk_15332.backup.jou 957B
webtalk_7392.backup.jou 956B
webtalk_20540.backup.jou 951B
webtalk_23044.backup.jou 951B
vivado.jou 810B
ISEWrap.js 7KB
rundef.js 1KB
runme.log 33KB
xvlog.log 2KB
compile.log 2KB
elaborate.log 1KB
webtalk_23760.backup.log 1KB
webtalk_15332.backup.log 1KB
webtalk.log 1KB
webtalk_7392.backup.log 1KB
webtalk_23044.backup.log 1020B
webtalk_20540.backup.log 1020B
summary.log 981B
summary.log 981B
summary.log 981B
summary.log 981B
summary.log 981B
summary.log 981B
summary.log 981B
summary.log 981B
summary.log 981B
summary.log 981B
simulate.log 941B
xsimkernel.log 343B
xsimkernel.log 333B
xsimcrash.log 0B
xsimcrash.log 0B
project_1.lpr 290B
xsim.mem 26KB
xsim.mem 14KB
xsim_0.win64.obj 85KB
xsim_0.win64.obj 68KB
xsim_1.win64.obj 7KB
xsim_1.win64.obj 6KB
elab.opt 218B
vivado.pb 53KB
xelab.pb 3KB
xvlog.pb 3KB
blk_mem_gen_0_utilization_synth.pb 224B
tb_picture_total_vlog.prj 338B
picture_total_vlog.prj 300B
vlog.prj 151B
xsim.reloc 22KB
xsim.reloc 12KB
xsim.rlx 838B
xsim.rlx 823B
xil_defaultlib.rlx 592B
blk_mem_gen_0_utilization_synth.rpt 6KB
.vivado.begin.rst 180B
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