没有合适的资源?快使用搜索试试~ 我知道了~
MSP-EXP430G2
3星 · 超过75%的资源 需积分: 35 14 下载量 100 浏览量
2017-12-26
16:16:27
上传
评论
收藏 1.51MB PDF 举报
温馨提示
试读
58页
MSP-EXP430G2原理图及。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。
资源推荐
资源详情
资源评论
MSP430G2x31
MSP430G2x21
www.ti.com
SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013
MIXED SIGNAL MICROCONTROLLER
1
FEATURES
• Low Supply-Voltage Range: 1.8 V to 3.6 V • 16-Bit Timer_A With Two Capture/Compare
Registers
• Ultra-Low Power Consumption
• Universal Serial Interface (USI) Supporting SPI
– Active Mode: 220 µA at 1 MHz, 2.2 V
and I2C (See Table 1)
– Standby Mode: 0.5 µA
• Brownout Detector
– Off Mode (RAM Retention): 0.1 µA
• 10-Bit 200-ksps A/D Converter With Internal
• Five Power-Saving Modes
Reference, Sample-and-Hold, and Autoscan
• Ultra-Fast Wake-Up From Standby Mode in
(See Table 1)
Less Than 1 µs
• Serial Onboard Programming,
• 16-Bit RISC Architecture, 62.5-ns Instruction
No External Programming Voltage Needed,
Cycle Time
Programmable Code Protection by Security
• Basic Clock Module Configurations
Fuse
– Internal Frequencies up to 16 MHz With
• On-Chip Emulation Logic With Spy-Bi-Wire
One Calibrated Frequency
Interface
– Internal Very Low Power Low-Frequency
• For Family Members Details, See Table 1
(LF) Oscillator
• Available in 14-Pin Plastic Small-Outline Thin
– 32-kHz Crystal
Package (TSSOP) (PW), 14-Pin Plastic Dual
– External Digital Clock Source Inline Package (PDIP) (N), and 16-Pin QFN
Package (RSA)
• For Complete Module Descriptions, See the
MSP430x2xx Family User’s Guide (SLAU144)
DESCRIPTION
The Texas Instruments MSP430 family of ultra-low-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.
The MSP430G2x21/G2x31 series is an ultra-low-power mixed signal microcontroller with a built-in 16-bit timer
and ten I/O pins. The MSP430G2x31 family members have a 10-bit A/D converter and built-in communication
capability using synchronous protocols (SPI or I2C). For configuration details, see Table 1.
Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values,
and then process the data for display or for transmission to a host system.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2010–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
MSP430G2x31
MSP430G2x21
SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013
www.ti.com
Table 1. Available Options
(1)
Flash RAM ADC10 Package
Device BSL EEM Timer_A USI Clock I/O
(KB) (B) Channel Type
(2)
MSP430G2231IRSA16 16-QFN
MSP430G2231IPW14 - 1 2 128 1x TA2 1 8 LF, DCO, VLO 10 14-TSSOP
MSP430G2231IN14 14-PDIP
MSP430G2221IRSA16 16-QFN
MSP430G2221IPW14 - 1 2 128 1x TA2 1 - LF, DCO, VLO 10 14-TSSOP
MSP430G2221IN14 14-PDIP
MSP430G2131IRSA16 16-QFN
MSP430G2131IPW14 - 1 1 128 1x TA2 1 8 LF, DCO, VLO 10 14-TSSOP
MSP430G2131IN14 14-PDIP
MSP430G2121IRSA16 16-QFN
MSP430G2121IPW14 - 1 1 128 1x TA2 1 - LF, DCO, VLO 10 14-TSSOP
MSP430G2121IN14 14-PDIP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
2 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
1
2
3
4
5
P1.4/SMCLK/TCK
6
P1.5/TA0.0/SCLK/TMS
7
P1.6/TA0.1/SDO/SCL/TDI/TCLK
8
P1.7/SDI/SDA/TDO/TDI
9
10
11
12
13
DVSS
14
DVSS
15
DVCC
16
DVCC
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3
XIN/P2.6/TA0.1
XOUT/P2.7
TEST/SBWTCK
RST/NMI/SBWTDIO
1
DVCC
2
3
4
5
6
7
8
P1.6/TA0.1/SDO/SCL/TDI/TCLK
9
P1.7/SDI/SDA/TDO/TDI
10
RST/NMI/SBWTDIO
11
TEST/SBWTCK
12
XOUT/P2.7
13
XIN/P2.6/TA0.1
14
DVSS
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3
P1.4/SMCLK/T CK
P1.5/TA0.0/SCLK/TMS
MSP430G2x31
MSP430G2x21
www.ti.com
SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013
Device Pinout, MSP430G2x21
N OR PW PACKAGE
(TOP VIEW)
NOTE: See port schematics in Application Information for detailed I/O information.
RSA PACKAGE
(TOP VIEW)
NOTE: See port schematics in Application Information for detailed I/O information.
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
1
2
3
4
5
P1.4/SMCLK/A4/VREF+/VEREF+/TCK
6
P1.5/TA0.0/SCLK/A5/TMS
7
P1.6/TA0.1/SDO/SCL/TDI/TCLK
8
P1.7/SDI/SDA/TDO/TDI
9
RST/NMI/SBWTDIO
10
TEST/SBWTCK
11
XOUT/P2.7
12
XIN/P2.6/TA0.1
13
DVSS
14
DVSS
15
DVCC
16
DVCC
P1.0/TA0CLK/ACLK/A0
P1.1/TA0.0/A1
P1.2/TA0.1/A2
P1.3/ADC10CLK/A3/VREF-/VEREF-
1
DVCC
2
3
4
5
6
7
8
P1.6/TA0.1/A6/SDO/SCL/TDI/TCLK
9
P1.7/A7/SDI/SDA/TDO/TDI
10
RST/NMI/SBWTDIO
11
TEST/SBWTCK
12
XOUT/P2.7
13
XIN/P2.6/TA0.1
14
DVSS
P1.0/TA0CLK/ACLK/A0
P1.1/TA0.0/A1
P1.2/TA0.1/A2
P1.3/ADC10CLK/A3/VREF-/VEREF-
P1.4/SMCLK/A4/VREF+/VEREF+/TCK
P1.5/TA0.0/A5/SCLK/TMS
MSP430G2x31
MSP430G2x21
SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013
www.ti.com
Device Pinout, MSP430G2x31
N OR PW PACKAGE
(TOP VIEW)
NOTE: See port schematics in Application Information for detailed I/O information.
RSA PACKAGE
(TOP VIEW)
NOTE: See port schematics in Application Information for detailed I/O information.
4 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Clock
System
Brownout
Protection
RST/NMI
DVCC DVSS
MCLK
Watchdog
WDT+
15-Bit
Timer0_A2
2 CC
Registers
16MHz
CPU
incl. 16
Registers
Emulation
2BP
JTAG
Interface
SMCLK
ACLK
MDB
MAB
Port P1
8 I/O
Interrupt
capability
pull-up/down
resistors
P1.x
8
Spy-Bi
Wire
XIN
XOUT
RAM
128B
Flash
2kB
1kB
ADC
10-Bit
8 Ch.
Autoscan
1 ch DMA
P2.x
Port P2
2 I/O
Interrupt
capability
pull-up/down
resistors
2
USI
Universal
Serial
Interface
SPI, I2C
Clock
System
Brownout
Protection
RST/NMI
DVCC DVSS
MCLK
Watchdog
WDT+
15-Bit
Timer0_A2
2 CC
Registers
16MHz
CPU
incl. 16
Registers
Emulation
2BP
JTAG
Interface
SMCLK
ACLK
MDB
MAB
Port P1
8 I/O
Interrupt
capability
pull-up/down
resistors
P1.x
8
Spy-Bi
Wire
XIN
XOUT
RAM
128B
Flash
2KB
1KB
P2.x
Port P2
2 I/O
Interrupt
capability
pull-up/down
resistors
2
USI
Universal
Serial
Interface
SPI, I2C
MSP430G2x31
MSP430G2x21
www.ti.com
SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013
Functional Block Diagram, MSP430G2x21
Functional Block Diagram, MSP430G2x31
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
剩余57页未读,继续阅读
资源评论
- gaominjie2019-08-03还可以,学习一下
qw186187
- 粉丝: 0
- 资源: 2
上传资源 快速赚钱
- 我的内容管理 展开
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功