Contents
1. Simulating Intel FPGA Designs......................................................................................11
1.1. Simulator Support................................................................................................11
1.2. Simulation Levels.................................................................................................12
1.3. HDL Support....................................................................................................... 12
1.4. Simulation Flows..................................................................................................13
1.5. Preparing for Simulation....................................................................................... 14
1.5.1. Compiling Simulation Models..................................................................... 14
1.6. Simulating Intel FPGA IP Cores.............................................................................. 15
1.6.1. Generating IP Simulation Files................................................................... 15
1.7. Using NativeLink Simulation (Intel Quartus Prime Standard Edition)............................17
1.7.1. Setting Up NativeLink Simulation (Intel Quartus Prime Standard Edition).........17
1.7.2. Running RTL Simulation (NativeLink Flow)...................................................18
1.7.3. Running Gate-Level Simulation (NativeLink Flow)......................................... 18
1.8. Running a Simulation (Custom Flow)...................................................................... 19
1.9. Document Revision History....................................................................................19
2. ModelSim - Intel FPGA Edition, ModelSim, and QuestaSim Support*.............................21
2.1. Quick Start Example (ModelSim with Verilog)...........................................................21
2.2. ModelSim, ModelSim-Intel FPGA Edition, and QuestaSim Guidelines............................22
2.2.1. Using ModelSim-Intel FPGA Edition Precompiled Libraries.............................. 22
2.2.2. Disabling Timing Violation on Registers....................................................... 22
2.2.3. Passing Parameter Information from Verilog HDL to VHDL............................. 23
2.2.4. Increasing Simulation Speed..................................................................... 23
2.2.5. Simulating Transport Delays...................................................................... 23
2.2.6. Viewing Simulation Messages.................................................................... 24
2.2.7. Generating Power Analysis Files................................................................. 25
2.2.8. Viewing Simulation Waveforms.................................................................. 25
2.2.9. Simulating with ModelSim-Intel FPGA Edition Waveform Editor.......................26
2.3. ModelSim Simulation Setup Script Example............................................................. 26
2.4. Unsupported Features.......................................................................................... 27
2.5. Document Revision History....................................................................................27
3. Synopsys VCS and VCS MX Support...............................................................................29
3.1. Quick Start Example (VCS with Verilog).................................................................. 29
3.2. VCS and QuestaSim Guidelines.............................................................................. 29
3.2.1. Simulating Transport Delays...................................................................... 30
3.2.2. Disabling Timing Violation on Registers....................................................... 30
3.2.3. Generating Power Analysis Files................................................................. 31
3.3. VCS Simulation Setup Script Example.....................................................................31
3.4. Document Revision History....................................................................................32
4. Cadence* Incisive Enterprise (IES) Support................................................................. 33
4.1. Quick Start Example (NC-Verilog)...........................................................................33
4.2. Cadence Incisive Enterprise (IES) Guidelines........................................................... 34
4.2.1. Using GUI or Command-Line Interfaces...................................................... 34
4.2.2. Elaborating Your Design............................................................................ 34
4.2.3. Back-Annotating Simulation Timing Data (VHDL Only)...................................35
4.2.4. Disabling Timing Violation on Registers....................................................... 35
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4.2.5. Simulating Pulse Reject Delays.................................................................. 35
4.2.6. Viewing Simulation Waveforms.................................................................. 36
4.3. IES Simulation Setup Script Example......................................................................36
4.4. Document Revision History....................................................................................37
5. Aldec* Active-HDL and Riviera-PRO Support.................................................................38
5.1. Quick Start Example (Active-HDL VHDL)................................................................. 38
5.2. Aldec Active-HDL and Riviera-PRO Guidelines.......................................................... 39
5.2.1. Compiling SystemVerilog Files................................................................... 39
5.2.2. Simulating Transport Delays...................................................................... 39
5.2.3. Disabling Timing Violation on Registers....................................................... 39
5.3. Using Simulation Setup Scripts.............................................................................. 40
5.4. Document Revision History....................................................................................40
6. Design Debugging Using In-System Sources and Probes.............................................. 41
6.1. Hardware and Software Requirements.................................................................... 43
6.2. Design Flow Using the In-System Sources and Probes Editor......................................43
6.2.1. Instantiating the In-System Sources and Probes IP Core............................... 44
6.2.2. In-System Sources and Probes IP Core Parameters.......................................45
6.3. Compiling the Design........................................................................................... 45
6.4. Running the In-System Sources and Probes Editor................................................... 46
6.4.1. In-System Sources and Probes Editor GUI................................................... 46
6.4.2. Programming Your Device With JTAG Chain Configuration.............................. 46
6.4.3. Instance Manager.................................................................................... 47
6.4.4. In-System Sources and Probes Editor Pane..................................................47
6.5. Tcl interface for the In-System Sources and Probes Editor......................................... 49
6.6. Design Example: Dynamic PLL Reconfiguration........................................................ 51
6.7. Document Revision History....................................................................................53
7. Timing Analysis Overview............................................................................................. 55
7.1. Timing Analysis Overview......................................................................................55
7.2. Timing Analyzer Terminology and Concepts............................................................. 55
7.2.1. Timing Netlists and Timing Paths................................................................55
7.2.2. Clock Setup Check................................................................................... 58
7.2.3. Clock Hold Check..................................................................................... 59
7.2.4. Recovery and Removal Time......................................................................60
7.2.5. Multicycle Paths....................................................................................... 61
7.2.6. Metastability........................................................................................... 62
7.2.7. Common Clock Path Pessimism Removal..................................................... 63
7.2.8. Clock-As-Data Analysis............................................................................. 64
7.2.9. Multicycle Clock Setup Check and Hold Check Analysis.................................. 66
7.2.10. Multicorner Analysis................................................................................69
7.3. Document Revision History....................................................................................70
8. The Intel Quartus Prime Timing Analyzer..................................................................... 71
8.1. Enhanced Timing Analysis for Intel Arria 10 Devices................................................. 71
8.2. Recommended Flow for First Time Users................................................................. 72
8.2.1. Creating and Setting Up your Design.......................................................... 72
8.2.2. Specifying Timing Requirements................................................................ 72
8.2.3. Performing a Full Compilation.................................................................... 74
8.2.4. Verifying Timing.......................................................................................75
8.2.5. Analyzing Timing in Designs Compiled in Previous Versions............................76
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8.3. Timing Constraints............................................................................................... 76
8.3.1. Recommended Starting SDC Constraints..................................................... 76
8.3.2. Creating Clocks and Clock Constraints........................................................ 82
8.3.3. Creating I/O Requirements........................................................................93
8.3.4. Creating Delay and Skew Constraints..........................................................95
8.3.5. Creating Timing Exceptions....................................................................... 99
8.3.6. A Sample Design with SDC File................................................................ 124
8.4. Running the Timing Analyzer............................................................................... 125
8.4.1. Intel Quartus Prime Settings....................................................................127
8.4.2. SDC File Precedence............................................................................... 127
8.5. Understanding Results........................................................................................ 128
8.5.1. Iterative Constraint Modification ..............................................................128
8.5.2. Set Operating Conditions Dialog Box......................................................... 129
8.5.3. Report Timing (Dialog Box)......................................................................131
8.5.4. Report CDC Viewer Command.................................................................. 131
8.5.5. Analyzing Results with Report Timing........................................................138
8.5.6. Correlating Constraints to the Timing Report..............................................141
8.6. Constraining and Analyzing with Tcl Commands......................................................145
8.6.1. Collection Commands............................................................................. 145
8.6.2. Identifying the Intel Quartus Prime Software Executable from the SDC File.... 148
8.6.3. Locating Timing Paths in Other Tools.........................................................149
8.7. Generating Timing Reports.................................................................................. 149
8.8. Document Revision History..................................................................................151
9. Power Analysis........................................................................................................... 153
9.1. Types of Power Analyses..................................................................................... 154
9.1.1. Differences between the EPE and the Intel Quartus Prime Power Analyzer......154
9.2. Factors Affecting Power Consumption....................................................................155
9.2.1. Device Selection.................................................................................... 155
9.2.2. Environmental Conditions........................................................................156
9.2.3. Device Resource Usage........................................................................... 157
9.2.4. Signal Activities..................................................................................... 157
9.3. Power Analyzer Flow...........................................................................................158
9.3.1. Operating Settings and Conditions............................................................158
9.3.2. Signal Activities Data Sources.................................................................. 159
9.4. Using Simulation Files in Modular Design Flows...................................................... 160
9.4.1. Complete Design Simulation.................................................................... 162
9.4.2. Modular Design Simulation...................................................................... 162
9.4.3. Multiple Simulations on the Same Entity....................................................163
9.4.4. Overlapping Simulations..........................................................................163
9.4.5. Partial Simulations................................................................................. 163
9.4.6. Node Name Matching Considerations ........................................................164
9.4.7. Glitch Filtering....................................................................................... 165
9.4.8. Node and Entity Assignments...................................................................166
9.4.9. Default Toggle Rate Assignment............................................................... 167
9.4.10. Vectorless Estimation............................................................................ 167
9.5. Using the Power Analyzer.................................................................................... 168
9.5.1. Common Analysis Flows.......................................................................... 168
9.5.2. Using .vcd for Power Estimation............................................................... 168
9.6. Power Analyzer Compilation Report ......................................................................170
9.7. Scripting Support............................................................................................... 172
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9.7.1. Running the Power Analyzer from the Command–Line................................. 172
9.8. Document Revision History..................................................................................173
10. System Debugging Tools Overview........................................................................... 175
10.1. System Debugging Tools Portfolio....................................................................... 175
10.1.1. System Debugging Tools Comparison...................................................... 175
10.1.2. System-Level Debugging Infrastructure...................................................176
10.1.3. Debugging Ecosystem........................................................................... 176
10.1.4. Tools to Analyze RTL Nodes....................................................................177
10.1.5. Suggested On-Chip Debugging Tools for Common Debugging Features........ 180
10.1.6. Stimulus-Capable Tools......................................................................... 181
10.2. Document Revision History................................................................................ 183
11. Analyzing and Debugging Designs with System Console........................................... 185
11.1. Introduction to System Console..........................................................................185
11.2. Debugging Flow with the System Console............................................................ 186
11.3. IP Cores that Interact with System Console..........................................................187
11.3.1. Services Provided through Debug Agents.................................................187
11.4. Starting System Console................................................................................... 188
11.4.1. Starting System Console from Nios II Command Shell............................... 188
11.4.2. Starting Stand-Alone System Console..................................................... 188
11.4.3. Starting System Console from Platform Designer (Standard)...................... 188
11.4.4. Starting System Console from Intel Quartus Prime....................................189
11.4.5. Customizing Startup............................................................................. 189
11.5. System Console GUI......................................................................................... 189
11.5.1. System Explorer Pane........................................................................... 190
11.6. System Console Commands...............................................................................191
11.7. Running System Console in Command-Line Mode................................................. 193
11.8. System Console Services...................................................................................194
11.8.1. Locating Available Services.................................................................... 194
11.8.2. Opening and Closing Services................................................................ 195
11.8.3. SLD Service.........................................................................................195
11.8.4. In-System Sources and Probes Service....................................................196
11.8.5. Monitor Service.................................................................................... 198
11.8.6. Device Service..................................................................................... 200
11.8.7. Design Service..................................................................................... 201
11.8.8. Bytestream Service.............................................................................. 202
11.8.9. JTAG Debug Service..............................................................................203
11.9. Working with Toolkits........................................................................................ 204
11.9.1. Convert your Dashboard Scripts to Toolkit API.......................................... 204
11.9.2. Creating a Toolkit Description File........................................................... 204
11.9.3. Registering a Toolkit............................................................................. 205
11.9.4. Launching a Toolkit............................................................................... 205
11.9.5. Matching Toolkits with IP Cores.............................................................. 206
11.9.6. Toolkit API........................................................................................... 206
11.10. ADC Toolkit....................................................................................................243
11.10.1. ADC Toolkit Terms...............................................................................246
11.10.2. Setting the Frequency of the Reference Signal....................................... 246
11.10.3. Tuning the Signal Generator.................................................................247
11.10.4. Running a Signal Quality Test............................................................... 249
11.10.5. Running a Linearity Test...................................................................... 250
Contents
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Quartus
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Prime Standard Edition Handbook Volume 3 Verification
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