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</script><title>Design Rule Verification Report</title>
</head>
<body onload=""><img ALT="Altium" src="
file://D:\Users\Public\Documents\Altium\AD20\Templates\AD_logo.png
"><h1>Design Rule Verification Report</h1>
<table class="header_holder">
<td class="column1">
<table class="front_matter">
<tr class="front_matter">
<td class="front_matter_column1">Date:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3">2023/2/28</td>
</tr>
<tr class="front_matter">
<td class="front_matter_column1">Time:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3">22:29:26</td>
</tr>
<tr class="front_matter">
<td class="front_matter_column1">Elapsed Time:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3">00:00:02</td>
</tr>
<tr class="front_matter">
<td class="front_matter_column1">Filename:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3"><a href="file:///D:\AD%E9%A1%B9%E7%9B%AE\bat\BAT.PcbDoc" class="file"><acronym title="D:\AD项目\bat\BAT.PcbDoc">D:\AD项目\bat\BAT.PcbDoc</acronym></a></td>
</tr>
</table>
</td>
<td class="column2">
<table class="DRC_summary_header">
<tr>
<td class="DRC_summary_header_col1">Warnings:</td>
<td class="DRC_summary_header_col2"></td>
<td class="DRC_summary_header_col3">0</td></tr>
<tr>
<td class="DRC_summary_header_col1">Rule Violations:</td>
<td class="DRC_summary_header_col2"></td>
<td class="DRC_summary_header_col3">0</td></tr>
</table>
</td>
</table><a name="IDJANRCYM2CFGRJF2NOLKYTROJRJTWQALOHN5DKY5SR4F0AO1RZMD"><h2>Summary</h2></a><table>
<tr>
<th class="column1">Warnings</th>
<th class="column2">Count</th>
</tr>
<tr>
<td style="font-weight : bold; text-align : right" class="column1">Total</td>
<td style="font-weight : bold" class="column2">0</td>
</tr>
</table><br><table>
<tr>
<th class="column1">Rule Violations</th>
<th class="column2">Count</th>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#ID4DQOQO41ZRKCMYLGKUTI5QECW30QNZSAIOMAPEACTJ5FYNX1BV">Clearance Constraint (Gap=6mil) (All),(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDSY45G5SQUPRJF4J05SAKA0CSFHD0N1N31RQWVRKOJXBXUA3MVWDP">Short-Circuit Constraint (Allowed=No) (All),(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDTGGOJV3ADQCQESCYNZZHGIUZMKSLKWA5HJVW3ZJLJSN2XQBQ3VXH">Un-Routed Net Constraint ( (All) )</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDLUKCMJLA3GRTFTBFFT05LV5UMDDI2XJQGFXXDPBKH1URUNGVQWIG">Modified Polygon (Allow modified: No), (Allow shelved: No)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#ID4UVAGM1NDETNDKOKUIIWMAAHDC4UGVRSZSMC54LLNXEV05TPI5HC">Width Constraint (Min=10mil) (Max=50mil) (Preferred=10mil) (All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDFOBUZ4VYWAHKM4TPILLVN0PFQEXLY0NBWM2EE3MS5IYMTMA5BK0M">Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)</a></td
bat.zip （34个子文件） 
bat 
bat.PrjPcb 37KB __Previews bat.SchDocPreview 393KB BAT.PcbDoc 6.04MB History 
bat.~(6).SchDoc.Zip 31KB BAT.~(9).PcbDoc.Zip 4.93MB BAT.~(20).PcbDoc.Zip 5.48MB BAT.~(22).PcbDoc.Zip 5.48MB bat.~(4).SchDoc.Zip 31KB BAT.~(8).PcbDoc.Zip 4.93MB BAT.~(21).PcbDoc.Zip 5.48MB bat.~(1).SchDoc.Zip 1KB BAT.~(16).PcbDoc.Zip 5.31MB BAT.~(19).PcbDoc.Zip 5.48MB BAT.~(6).PcbDoc.Zip 4.9MB BAT.~(18).PcbDoc.Zip 5.44MB BAT.~(5).PcbDoc.Zip 4.9MB BAT.~(4).PcbDoc.Zip 4.95MB bat.~(5).SchDoc.Zip 31KB bat.~(7).SchDoc.Zip 33KB BAT.~(7).PcbDoc.Zip 4.93MB BAT.~(1).PcbDoc.Zip 24KB BAT.~(23).PcbDoc.Zip 5.48MB 00000000ECFF17CF Copy of bat.~(3).SchDoc.Zip 33KB Copy of bat.~(1).SchDoc.Zip 33KB Copy of bat.~(2).SchDoc.Zip 33KB BAT.~(17).PcbDoc.Zip 5.44MB bat.SchDoc 246KB Project Outputs for bat Design Rule Check - BAT.drc 1KB
Design Rule Check - BAT.html 10KB Project Logs for bat bat SCH ECO 2023-2-11 23-42-03.LOG 3KB BAT PCB ECO 2023-2-11 23-57-26.LOG 35KB Copy of bat SCH ECO 2023-2-26 19-59-49.LOG 2KB BAT PCB ECO 2023-2-26 20-01-06.LOG 6KB bat SCH ECO 2023-2-11 23-50-44.LOG 0B资源评论
