j3环视q111111

环视max96722解串器最终配置

环视解串器最终配置

1.//max96712_quad_init_setting_base

i2ctransfer -y -f 1 w3@0x29 0x04 0x0B 0x00 //disable mipi output CSI output

disabled

i2ctransfer -y -f 1 w3@0x29 0x06 0xc2 0x10

i2ctransfer -y -f 1 w3@0x29 0x16 0xd1 0x03

i2ctransfer -y -f 1 w3@0x29 0x17 0xd1 0x03

i2ctransfer -y -f 1 w3@0x29 0x00 0x10 0x11 //set 3 g

i2ctransfer -y -f 1 w3@0x29 0x00 0x11 0x11

i2ctransfer -y -f 1 w3@0x29 0x00 0x18 0x0f //one shot

i2ctransfer -y -f 1 w3@0x29 0x00 0x06 0xff //enable 4 links in gmsl2 mode

Enable all 4 Links & GMSL2 mode

i2ctransfer -y -f 1 w3@0x29 0x00 0xf0 0x62 //link A ->pipe 0, link B->pipe1 pipe

select pipe Z in link B to video pipe 1, pipe Z in link A to video pipe

i2ctransfer -y -f 1 w3@0x29 0x00 0xf1 0xea //link C->pipe 2, link D->pipe3

Turn on all pipeS 8

i2ctransfer -y -f 1 w3@0x29 0x08 0xa2 0xF4 // Enable MIPI PHY0~3

Enable MIPI PHY0 ~ PHY3 # Turn on MIPI PHYs

2.//des_data_lane_setting

i2ctransfer -y -f 1 w3@0x29 0x08 0xa0 0x04 //Set Des in 2x4 mode

i2ctransfer -y -f 1 w3@0x29 0x08 0xa3 0xe4 //Set Lane Mapping for 4-lane port A //

Map data lanes for PHY 1 map PHY0-D0D1 phy1-D2D3 (2-4lanes) #Set Lane Mapping for 4-

lane port A

i2ctransfer -y -f 1 w3@0x29 0x08 0xa4 0xe4 // Map data lanes for PHY 0

i2ctransfer -y -f 1 w3@0x29 0x09 0x0b 0x07 // Map source 0~2 for Link A

i2ctransfer -y -f 1 w3@0x29 0x09 0x2d 0x15 // Map source to controller 1 map

MAP_DPHY_DEST to MIPI Controller 1 ---MAP_DPHY_DEST0~2 PORTA

i2ctransfer -y -f 1 w3@0x29 0x09 0x0d 0x1e // src vc && datatype, vc = 0, YUV422

map SRC0 data to VC0 YUV422

i2ctransfer -y -f 1 w3@0x29 0x09 0x0e 0x1e //map to vc0 // dst vc && datatype, vc =

0, YUV422 map DES0 data to VC0

i2ctransfer -y -f 1 w3@0x29 0x09 0x0f 0x00 // src frame start

i2ctransfer -y -f 1 w3@0x29 0x09 0x10 0x00 // dst frame start

i2ctransfer -y -f 1 w3@0x29 0x09 0x4e 0x5e //map to v1

i2ctransfer -y -f 1 w3@0x29 0x09 0x4f 0x00

i2ctransfer -y -f 1 w3@0x29 0x09 0x50 0x40

i2ctransfer -y -f 1 w3@0x29 0x09 0x51 0x01

i2ctransfer -y -f 1 w3@0x29 0x09 0x52 0x41

i2ctransfer -y -f 1 w3@0x29 0x09 0x8b 0x07 // Map source 0~2 for Link C

i2ctransfer -y -f 1 w3@0x29 0x09 0xad 0x15

i2ctransfer -y -f 1 w3@0x29 0x09 0x8d 0x1e

i2ctransfer -y -f 1 w3@0x29 0x09 0x8e 0x9e //map to v2

i2ctransfer -y -f 1 w3@0x29 0x09 0xed 0x15

i2ctransfer -y -f 1 w3@0x29 0x09 0xcd 0x1e

i2ctransfer -y -f 1 w3@0x29 0x09 0xce 0xde //map to v3

i2ctransfer -y -f 1 w3@0x29 0x09 0xcf 0x00

i2ctransfer -y -f 1 w3@0x29 0x09 0xd0 0xc0

i2ctransfer -y -f 1 w3@0x29 0x09 0xd1 0x01

i2ctransfer -y -f 1 w3@0x29 0x09 0xd2 0xc1

3.//des_data_rate_setting // Hold DPLL in reset (config_soft_rst_n = 0) before

changing the rate