CPU模块的Verilog HDL源代码框架-供参考
module cpu_design (reset, clock, write_read, M_address, M_data_in, M_data_out,overflow);
input reset,clock;
input[7:0] M_data_in;
output reg write_read,overflow;
output reg [7:0] M_data_out;
output reg[11:0] M_address;
reg[15:0] IR;
reg[7:0] MDR;
reg[11:0] MAR,PC;
…. //补充完整相关中间变量
reg[2:0] status;
parameter idle=4'b0000, load=4'b0001, move=4'b0010, …….//补充完整所有指令操作码
always@(reset or status) // process the read and write operation for main memory.
begin
if((reset==1)&&(status==3)&&(IR[15:12]==write))
write_read=1'b1;//write opeartion
else
write_read=1'b0;//read operation
M_address=MAR;
M_data_out=MDR;
Overflow=1’b0;
If …
//补充overflow标志位的处理，overflow仅在进行加、减运算时才可能为1.
end
always @(negedge clock or negedge reset)// status_change process, status machine
begin
if(reset==1'b0) status<=3'b000;// valid reset signal is 0
else if(clock==1'b0)// descend edge of clock
case (status)
3'b000: begin
status<=1;
MAR<=PC;
Case(IR[9:8])
2’b00: A<=R0;
2’b01: A<=R1;
….//补充完整
endcase
end
