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i.MX 8M Plus Applications Processor
Reference Manual
Document Number: IMX8MPRM
Rev. 1, 06/2021
i.MX 8M Plus Applications Processor Reference Manual, Rev. 1, 06/2021
2 NXP Semiconductors
Contents
Section number Title Page
Chapter 1
Introduction
1.1 Product Overview ........................................................................................................................................................ 9
1.2 Target Applications.......................................................................................................................................................9
1.3 Acronyms and Abbreviations....................................................................................................................................... 9
1.4 Architectural Overview.................................................................................................................................................12
Chapter 2
Memory Map
2.1 Memory system overview.............................................................................................................................................23
2.2 Cortex-A53 Memory Map ........................................................................................................................................... 24
2.3 Cortex-M7 Memory Map..............................................................................................................................................26
2.4 DMA memory maps..................................................................................................................................................... 29
2.5 AIPS Memory Maps..................................................................................................................................................... 30
2.6 DAP Memory Map....................................................................................................................................................... 36
2.7 Audio Processor Memory Map.....................................................................................................................................38
2.8 HDMI_TX Subsystem Memory Map........................................................................................................................... 38
Chapter 3
Security
3.1 System Security............................................................................................................................................................ 41
3.2 Resource Domain Controller (RDC)............................................................................................................................ 44
Chapter 4
Arm Platform and Debug
4.1 Arm Cortex A53 Platform (A53)..................................................................................................................................91
4.2 Arm Cortex M7 Platform (CM7)..................................................................................................................................97
4.3 Messaging Unit (MU)...................................................................................................................................................99
4.4 Semaphore (SEMA4)....................................................................................................................................................143
4.5 On-Chip RAM Memory Controller (OCRAM)............................................................................................................161
4.6 Network Interconnect Bus System (NIC).....................................................................................................................164
i.MX 8M Plus Applications Processor Reference Manual, Rev. 1, 06/2021
NXP Semiconductors 3
Section number Title Page
4.7 AHB to IP Bridge (AIPSTZ)........................................................................................................................................ 165
4.8 Shared Peripheral Bus Arbiter (SPBA).........................................................................................................................188
4.9 TrustZone Address Space Controller (TZASC)........................................................................................................... 201
4.10 System Debug...............................................................................................................................................................203
4.11 System Counter (SYS_CTR)........................................................................................................................................207
Chapter 5
Clocks and Power Management
5.1 Clock Control Module (CCM)......................................................................................................................................227
5.2 General Power Controller (GPC)..................................................................................................................................566
5.3 Crystal Oscillator (XTALOSC).................................................................................................................................... 718
5.4 Thermal Monitoring Unit (TMU)................................................................................................................................. 722
Chapter 6
SNVS, Reset, Fuse, and Boot
6.1 System Boot..................................................................................................................................................................741
6.2 Fusemap........................................................................................................................................................................808
6.3 On-Chip OTP Controller (OCOTP_CTRL)..................................................................................................................824
6.4 Secure Non-Volatile Storage (SNVS).......................................................................................................................... 868
6.5 System Reset Controller (SRC).................................................................................................................................... 897
6.6 Watchdog Timer (WDOG)........................................................................................................................................... 968
Chapter 7
Interrupts and DMA
7.1 Interrupts and DMA Events..........................................................................................................................................987
7.2 Smart Direct Memory Access Controller (SDMA)...................................................................................................... 1008
7.3 Enhanced Direct Memory Access (eDMA)..................................................................................................................1256
7.4 Interrupt Request Steering (IRQ_STEER)....................................................................................................................1318
Chapter 8
Chip IO and Pinmux
8.1 External Signals and Pin Multiplexing......................................................................................................................... 1329
8.2 IOMUX Controller (IOMUXC)....................................................................................................................................1352
8.3 General Purpose Input/Output (GPIO)......................................................................................................................... 1982
i.MX 8M Plus Applications Processor Reference Manual, Rev. 1, 06/2021
4 NXP Semiconductors
Section number Title Page
Chapter 9
External Memory
9.1 External Memory Overview......................................................................................................................................... 2001
9.2 DDR Controller (DDRC)..............................................................................................................................................2003
9.3 DDR BLK_CTRL.........................................................................................................................................................2164
9.4 DDR PHY (DDR_PHY)...............................................................................................................................................2166
9.5 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA).......................................................................................... 2177
9.6 62BIT Correcting ECC Accelerator (BCH)..................................................................................................................2217
9.7 General Purpose Media Interface (GPMI)....................................................................................................................2280
Chapter 10
Mass Storage
10.1 Enhanced Configurable SPI (ECSPI)........................................................................................................................... 2339
10.2 FlexSPI Controller (FlexSPI)........................................................................................................................................2369
10.3 Ultra Secured Digital Host Controller (uSDHC)..........................................................................................................2500
Chapter 11
Connectivity
11.1 HSIO BLK_CTRL........................................................................................................................................................2659
11.2 Universal Serial Bus Controller (USB).........................................................................................................................2680
11.3 Universal Serial Bus PHY (USB_PHY).......................................................................................................................2993
11.4 PCI Express (PCIe).......................................................................................................................................................2997
11.5 PCI Express PHY (PCIe_PHY)....................................................................................................................................3369
11.6 Ethernet MAC (ENET).................................................................................................................................................3754
11.7 Ethernet Quality Of Service (ENET_QOS) .................................................................................................................3957
11.8 FlexCAN.......................................................................................................................................................................4980
Chapter 12
Timers
12.1 General Purpose Timer (GPT)......................................................................................................................................5123
12.2 Pulse Width Modulation (PWM)..................................................................................................................................5142
Chapter 13
Display, Imaging, and Camera
i.MX 8M Plus Applications Processor Reference Manual, Rev. 1, 06/2021
NXP Semiconductors 5
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