################################################################################
# Vivado (TM) v2021.1 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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FPGA控制AD9767实现DDS输出
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2023-03-16
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硬件平台:XC7A35T 软件平台:VIVADO2021.1 资源实现了通过FPGA控制AD9767来制作一个建议的DDS信号发生器。其中设置了是否开启扫频模式,扫频可设步长以及起止频率,扫频模式固定为向下扫频。扫频间隔为1s,也可以修改。本设计可结合本人的两篇博客快速上手,轻松控制AD9767产生波形信号。同时,对于传统控制法控制DDS信号发生器本设计做出了修改,修复了输出频率抖动的问题,详情可参考相关系列博客第二篇,以下附上链接:https://blog.csdn.net/qq_46284844/article/details/129580026?spm=1001.2014.3001.5501 如果没有积分的朋友可以通过第二篇文章的最后百度网盘链接获取。
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FPGA控制AD9767实现DDS输出 (411个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
_info 4KB
_info 170B
_info 170B
_vmake 29B
xsim.ini.bak 28KB
elaborate.bat 2KB
compile.bat 1KB
simulate.bat 816B
compile.bat 810B
runme.bat 229B
runme.bat 229B
runme.bat 229B
xsim_2.c 143KB
dds_square_4096x14b_wave.coe 26KB
dds_square_4096x14b_wave.coe 26KB
dds_square_4096x14b_wave.coe 26KB
dds_square_4096x14b_wave.coe 26KB
dds_square_4096x14b_wave.coe 26KB
dds_square_4096x14b_wave.coe 26KB
dds_square_4096x14b_wave.coe 26KB
dds_square_4096x14b_wave.coe 26KB
dds_square_4096x14b_wave.coe 26KB
dds_square_4096x14b_wave.coe 26KB
dds_square_4096x14b_wave.coe 26KB
dds_square_4096x14b_wave.coe 26KB
ssm.db 572B
div_gen_0.dcp 1.94MB
div_gen_0.dcp 1.94MB
div_gen_0.dcp 1.94MB
div_gen_0.dcp 1.87MB
div_gen_0.dcp 1.08MB
AD9767_test2.dcp 41KB
blk_mem_gen_0.dcp 36KB
blk_mem_gen_0.dcp 36KB
blk_mem_gen_0.dcp 36KB
compile.do 3KB
compile.do 3KB
compile.do 3KB
tb_ad9767_compile.do 970B
tb_ad9767_simulate.do 892B
compile.do 804B
compile.do 788B
compile.do 714B
compile.do 700B
simulate.do 618B
simulate.do 618B
simulate.do 572B
elaborate.do 446B
simulate.do 390B
simulate.do 389B
simulate.do 389B
tb_ad9767_wave.do 342B
compile.do 260B
simulate.do 252B
simulate.do 244B
elaborate.do 213B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 12B
simulate.do 11B
simulate.do 11B
run.f 2KB
run.f 2KB
run.f 541B
run.f 521B
modelsim.ini 133KB
modelsim.ini 133KB
xsim.ini 28KB
xsim.ini 27KB
xsim.ini 27KB
vivado.jou 902B
vivado.jou 861B
vivado_18416.backup.jou 855B
vivado.jou 833B
vivado_12200.backup.jou 815B
vivado.jou 815B
ISEWrap.js 8KB
ISEWrap.js 8KB
ISEWrap.js 8KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
simulate.log 35KB
runme.log 34KB
runme.log 20KB
runme.log 17KB
elaborate.log 15KB
compile.log 2KB
vivado.log 1KB
vivado_18416.backup.log 1KB
summary.log 904B
summary.log 904B
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