/*!
\file gd32f10x_enet.c
\brief ENET driver
\version 2014-12-26, V1.0.0, firmware for GD32F10x
\version 2017-06-20, V2.0.0, firmware for GD32F10x
\version 2018-07-31, V2.1.0, firmware for GD32F10x
\version 2020-09-30, V2.2.0, firmware for GD32F10x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32f10x_enet.h"
#ifdef GD32F10X_CL
#if defined (__CC_ARM) /*!< ARM compiler */
__align(4)
enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */
__align(4)
enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */
__align(4)
uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */
__align(4)
uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */
#elif defined ( __ICCARM__ ) /*!< IAR compiler */
#pragma data_alignment=4
enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */
#pragma data_alignment=4
enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */
#pragma data_alignment=4
uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */
#pragma data_alignment=4
uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */
#elif defined (__GNUC__) /* GNU Compiler */
enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM] __attribute__ ((aligned (4))); /*!< ENET RxDMA descriptor */
enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM] __attribute__ ((aligned (4))); /*!< ENET TxDMA descriptor */
uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE] __attribute__ ((aligned (4))); /*!< ENET receive buffer */
uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE] __attribute__ ((aligned (4))); /*!< ENET transmit buffer */
#endif /* __CC_ARM */
/* global transmit and receive descriptors pointers */
enet_descriptors_struct *dma_current_txdesc;
enet_descriptors_struct *dma_current_rxdesc;
/* structure pointer of ptp descriptor for normal mode */
enet_descriptors_struct *dma_current_ptp_txdesc = NULL;
enet_descriptors_struct *dma_current_ptp_rxdesc = NULL;
/* init structure parameters for ENET initialization */
static enet_initpara_struct enet_initpara ={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
static uint32_t enet_unknow_err = 0U;
/* array of register offset for debug information get */
static const uint16_t enet_reg_tab[] = {
0x0000, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x1080, 0x001C, 0x0028, 0x002C,
0x0038, 0x003C, 0x0040, 0x0044, 0x0048, 0x004C, 0x0050, 0x0054, 0x0058, 0x005C,
0x0100, 0x0104, 0x0108, 0x010C, 0x0110, 0x014C, 0x0150, 0x0168, 0x0194, 0x0198, 0x01C4,
0x0700, 0x0704,0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x071C, 0x0720,
0x1000, 0x1004, 0x1008, 0x100C, 0x1010, 0x1014, 0x1018, 0x101C, 0x1020, 0x1048, 0x104C,
0x1050, 0x1054};
/*!
\brief deinitialize the ENET, and reset structure parameters for ENET initialization
\param[in] none
\param[out] none
\retval none
*/
void enet_deinit(void)
{
rcu_periph_reset_enable(RCU_ENETRST);
rcu_periph_reset_disable(RCU_ENETRST);
enet_initpara_reset();
}
/*!
\brief configure the parameters which are usually less cared for initialization
note -- this function must be called before enet_init(), otherwise
configuration will be no effect
\param[in] option: different function option, which is related to several parameters,
only one parameter can be selected which is shown as below, refer to enet_option_enum
\arg FORWARD_OPTION: choose to configure the frame forward related parameters
\arg DMABUS_OPTION: choose to configure the DMA bus mode related parameters
\arg DMA_MAXBURST_OPTION: choose to configure the DMA max burst related parameters
\arg DMA_ARBITRATION_OPTION: choose to configure the DMA arbitration related parameters
\arg STORE_OPTION: choose to configure the store forward mode related parameters
\arg DMA_OPTION: choose to configure the DMA descriptor related parameters
\arg VLAN_OPTION: choose to configure vlan related parameters
\arg FLOWCTL_OPTION: choose to configure flow control related parameters
\arg HASHH_OPTION: choose to configure hash high
\arg HASHL_OPTION: choose to configure hash low
\arg FILTER_OPTION: choose to configure frame filter related parameters
\arg HALFDUPLEX_OPTION: choose to configure halfduplex mode related parameters
\arg TIMER_OPTION: choose to configure time counter related parameters
\arg INTERFRAMEGAP_OPTION: choose to configure the inter frame gap related parameters
\param[in] para: the related parameters according to the option
all the related parameters should be configured which are shown as below
FORWARD_OPTION related parameters:
- ENET_AUTO_PADCRC_DROP_ENABLE/ ENET_AUTO_PADCRC_DROP_DISABLE ;
- ENET_FORWARD_ERRFRAMES_ENABLE/ ENET_FORWARD_ERRFRAMES_DISABLE ;
- ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE/ ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE .
DMABUS_OPTION related parameters:
- ENET_ADDRESS_ALIGN_ENABLE/ ENET_ADDRESS_ALIGN_DISABLE ;
- ENET_FIXED_BURST_ENABLE/ ENET_FIXED_BURST_DISABLE ;
DMA_MAXBURST_OPTION related parameters:
- ENET_RXDP_1BEAT/ ENET_RXDP_2BEAT/ ENET_RXDP_4BEAT/
ENET_RXDP_8BEAT/ ENET_RXDP_16BEAT/ ENET_RXDP_32BEAT/
ENET_RXDP_4xPGBL_4BEAT/ ENET_RXDP_4xPGBL_8BEAT/
ENET_RXDP_4xPGBL_16BEAT/ ENET_RXDP_4xPGBL_32BEAT/
ENET_RXDP_4xPGBL_64BEAT/ ENET_RXDP_4xPGBL_128BEAT ;
- ENET_PGBL_1BEAT/ ENET_PGBL_2BEAT/ ENET_PGBL_4BEAT/
ENET_PGBL_8BEAT/ ENET_PGBL_16BEAT/ ENET_PGBL_32BEAT/
ENET_PGBL_4xPGBL_4BEAT/ ENET_PGBL_4xPGBL_8BEAT/
ENET_PGBL_
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gd32f103工程搭建万能模板
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gd32f103工程搭建万能模板 (224个子文件)
walk.uvguix.Administrator 89KB
walk.axf 102KB
walk.axf 36KB
gd32f10x_enet.c 130KB
gd32f10x_timer.c 85KB
gd32f10x_rcu.c 42KB
gd32f10x_can.c 42KB
gd32f10x_adc.c 37KB
system_gd32f10x.c 33KB
gd32f10x_fmc.c 31KB
gd32f10x_exmc.c 30KB
gd32f10x_sdio.c 28KB
gd32f10x_dma.c 28KB
gd32f10x_usart.c 25KB
gd32f10x_i2c.c 25KB
gd32f10x_spi.c 24KB
gd32f10x_gpio.c 20KB
gd32f10x_dac.c 16KB
gd32f10x_exti.c 8KB
gd32f10x_rtc.c 8KB
gd32f10x_pmu.c 8KB
gd32f10x_bkp.c 8KB
gd32f10x_misc.c 7KB
gd32f10x_fwdgt.c 7KB
gd32f10x_dbg.c 6KB
gd32f10x_wwdgt.c 4KB
gd32f10x_crc.c 4KB
gd32f10x_it.c 4KB
main.c 3KB
systick.c 3KB
spi.c 1KB
gd32f10x_timer.crf 293KB
gd32f10x_can.crf 282KB
gd32f10x_fmc.crf 281KB
gd32f10x_adc.crf 281KB
gd32f10x_rcu.crf 279KB
gd32f10x_exmc.crf 279KB
gd32f10x_dma.crf 278KB
gd32f10x_usart.crf 278KB
gd32f10x_i2c.crf 277KB
gd32f10x_spi.crf 276KB
gd32f10x_dac.crf 276KB
gd32f10x_sdio.crf 276KB
gd32f10x_gpio.crf 276KB
system_gd32f10x.crf 274KB
gd32f10x_bkp.crf 273KB
gd32f10x_pmu.crf 273KB
gd32f10x_exti.crf 273KB
gd32f10x_rtc.crf 273KB
gd32f10x_fwdgt.crf 273KB
gd32f10x_misc.crf 272KB
gd32f10x_crc.crf 272KB
main.crf 272KB
gd32f10x_dbg.crf 272KB
gd32f10x_it.crf 272KB
gd32f10x_wwdgt.crf 272KB
spi.crf 272KB
systick.crf 271KB
gd32f10x_enet.crf 271KB
gd32f10x_wwdgt.d 2KB
gd32f10x_timer.d 2KB
gd32f10x_fwdgt.d 2KB
gd32f10x_usart.d 2KB
gd32f10x_gpio.d 2KB
gd32f10x_exti.d 2KB
gd32f10x_sdio.d 2KB
gd32f10x_exmc.d 2KB
gd32f10x_misc.d 2KB
gd32f10x_enet.d 2KB
system_gd32f10x.d 2KB
gd32f10x_crc.d 2KB
gd32f10x_rtc.d 2KB
gd32f10x_can.d 2KB
gd32f10x_adc.d 2KB
gd32f10x_fmc.d 2KB
gd32f10x_rcu.d 2KB
gd32f10x_dma.d 2KB
gd32f10x_dac.d 2KB
gd32f10x_dbg.d 2KB
gd32f10x_spi.d 2KB
gd32f10x_bkp.d 2KB
gd32f10x_pmu.d 2KB
gd32f10x_i2c.d 2KB
gd32f10x_it.d 2KB
systick.d 2KB
main.d 2KB
spi.d 2KB
gd32f10x_it.d 1KB
system_gd32f10x.d 1KB
gd32f10x_wwdgt.d 1KB
gd32f10x_timer.d 1KB
gd32f10x_fwdgt.d 1KB
gd32f10x_usart.d 1KB
gd32f10x_gpio.d 1KB
gd32f10x_exti.d 1KB
gd32f10x_sdio.d 1KB
gd32f10x_exmc.d 1KB
gd32f10x_misc.d 1KB
gd32f10x_enet.d 1KB
gd32f10x_crc.d 1KB
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