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ADV7401_Manual_RevB.pdf
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ADV7401_Manual_RevB.pdf详细推荐配置
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ADV7401
Integrated Multi-Format SDTV/HDTV
Video Decoder and RGB Graphics
Digitizer
DATASHEET
MANUAL
January 2007
ADV7401
1 INTRODUCTION..................................................................................................................................................... 1
1.1 Analogue Front-end........................................................................................................................................... 1
1.2 Standard Definition Processor ........................................................................................................................... 1
1.3 Component Processor ........................................................................................................................................ 2
1.4 Detailed Functionality of ADV7401.................................................................................................................. 3
1.4.1 Analogue Front End...................................................................................................................................... 3
1.4.2 User Programmable Video Output Formats.................................................................................................. 3
1.4.3 Composite and S-Video Processing.............................................................................................................. 3
1.4.4 Component Video Processing....................................................................................................................... 4
1.4.5 RGB Graphics Processing............................................................................................................................. 5
1.4.6 Digital Video Input Port................................................................................................................................ 5
1.4.7 Additional Features....................................................................................................................................... 5
1.5 Applications....................................................................................................................................................... 6
1.6 Functional Block Diagram................................................................................................................................. 7
1.7 Pin Description .................................................................................................................................................. 8
1.8 Absolute Maximum Ratings ............................................................................................................................ 11
1.9 Ordering Guide................................................................................................................................................ 11
1.10 ESD Caution.................................................................................................................................................... 12
2 ANALOGUE FRONT END ................................................................................................................................... 13
2.1 Analogue Input Muxing................................................................................................................................... 13
2.1.1 ADI Recommended Input Muxing ............................................................................................................. 14
2.1.2 ADI Recommended Applications HD, PR, GR and SD ............................................................................. 15
2.1.3 Alternative Applications SD ....................................................................................................................... 17
2.1.4 Manual Input Muxing ................................................................................................................................. 19
2.2 Bias Current Control........................................................................................................................................ 22
2.2.1 Bias Current Setting.................................................................................................................................... 22
2.2.2 Xtal Clock Input Pin Functionality ............................................................................................................. 22
2.2.3 EN28XTAL Enable 28.63636 MHz Crystal Operation .............................................................................. 23
2.3 Anti Alias Filters ............................................................................................................................................. 23
2.4 SCART and Fast Blanking .............................................................................................................................. 25
2.4.1 System Diagram.......................................................................................................................................... 25
2.4.2 Top Level Control....................................................................................................................................... 26
2.4.3 Contrast Reduction...................................................................................................................................... 28
2.4.4 Readback of FB Pin Status.......................................................................................................................... 30
2.4.5 FB Timing................................................................................................................................................... 31
3 PRIMARY MODE AND VIDEO STANDARD ................................................................................................... 33
4 GLOBAL CONTROL REGISTERS..................................................................................................................... 37
4.1 Power-save Modes........................................................................................................................................... 37
4.1.1 Power-Down ............................................................................................................................................... 37
4.1.2 Power-save Mode........................................................................................................................................ 38
4.1.3 ADC Power-down Control.......................................................................................................................... 38
4.2 Reset Control ................................................................................................................................................... 39
4.3 Global Pin Control........................................................................................................................................... 40
4.3.1 Tristate Output Drivers ............................................................................................................................... 40
4.3.2 Tristate LLC Driver .................................................................................................................................... 40
4.3.3 Timing Signals Output Enable.................................................................................................................... 40
4.3.4 Drive Strength Selection (Data).................................................................................................................. 41
4.3.5 Drive Strength Selection (Clock)................................................................................................................ 41
4.3.6 Drive Strength Selection (Synchronization) ............................................................................................... 42
4.3.7 Enable Subcarrier Frequency Lock Pin....................................................................................................... 42
4.3.8 Polarity LLC Pin......................................................................................................................................... 42
5 GLOBAL STATUS REGISTERS ......................................................................................................................... 43
5.1 Identification.................................................................................................................................................... 43
5.2 STATUS 1 ....................................................................................................................................................... 43
ADV7401
5.2.1 SDP Autodetection Result .......................................................................................................................... 44
5.3 STATUS 2 ....................................................................................................................................................... 44
5.4 STATUS 3 ....................................................................................................................................................... 45
6 COMPONENT PROCESSOR............................................................................................................................... 46
6.1 Introduction to Component Processor ............................................................................................................. 46
6.2 Data Delay Block (CP) .................................................................................................................................... 47
6.3 Analogue Video Signal Sampling.................................................................................................................... 47
6.3.1 CP PLL Control .......................................................................................................................................... 48
6.3.2 Manual PLL Divider Ratio Value............................................................................................................... 48
6.3.3 PLL Divide Ratio and DLL Phase Update Sequencing .............................................................................. 49
6.3.4 CP VCO Range Setting............................................................................................................................... 49
6.3.5 PLL Charge Pump Setting .......................................................................................................................... 51
6.3.6 Recommended Settings for CP PLL Modes of Operation .......................................................................... 52
6.3.7 Non Standard CP PLL Modes of Operation................................................................................................ 53
6.4 ADC Sampling Phase Control ......................................................................................................................... 53
6.4.1 Delay Locked Loop..................................................................................................................................... 54
6.4.2 Latch Clock Setting..................................................................................................................................... 55
6.4.3 Embedded Synchronization Slicer .............................................................................................................. 56
6.5 Data Preprocessors........................................................................................................................................... 58
6.5.1 Color Space Conversion Matrix.................................................................................................................. 58
6.5.2 DPP Decimation Filters .............................................................................................................................. 65
6.6 Clamp Operation (CP) ..................................................................................................................................... 72
6.7 Component Processor Gain Operation............................................................................................................. 75
6.7.1 Automatic Gain Control.............................................................................................................................. 76
6.7.2 Manual Gain Control .................................................................................................................................. 79
6.7.3 Manual Gain FILTER Mode....................................................................................................................... 80
6.7.4 CP Peak Active Video Readback................................................................................................................ 80
6.8 Component Processor Offset Block................................................................................................................. 82
6.9 AV Code Block (CP)....................................................................................................................................... 84
6.10 Synchronization Source Polarity Detector....................................................................................................... 86
6.10.1 SSPD Readback Signals......................................................................................................................... 89
6.11 External Digital Synchronization Input Pins (CP)........................................................................................... 90
6.12 External Clock Input Control........................................................................................................................... 90
6.13 CP Output Synchronization Signal Positioning............................................................................................... 90
6.13.1 CP Primary Synchronization Signals ..................................................................................................... 91
6.13.2 HS Timing Controls (CP)....................................................................................................................... 92
6.13.3 VS Timing Controls (CP)....................................................................................................................... 95
6.13.4 FIELD Timing Controls (CP) ................................................................................................................ 96
6.13.5 240p, 540p, 1080p, and 1250p Support................................................................................................ 104
6.13.6 Secondary Synchronization Signals (CP)............................................................................................. 104
6.13.7 Ancillary Synchronization Signal Output (CP)....................................................................................105
6.14 Standard Detection and Identification ........................................................................................................... 107
6.14.1 STDI Usage.......................................................................................................................................... 110
6.14.2 STDI Readback Values for SD, PR and HD ........................................................................................ 111
6.14.3 STDI Readback Values for GR (Normal and Improved Modes) ......................................................... 113
6.15 Component Processor Horizontal Lock Status .............................................................................................. 114
6.16 Component Processor VBI Data Support ...................................................................................................... 116
7 STANDARD DEFINITION PROCESSOR ........................................................................................................ 119
7.1 SD Luma Path................................................................................................................................................ 119
7.2 SD Chroma Path ............................................................................................................................................ 120
7.3 SDP Synchronization Processing................................................................................................................... 120
7.4 SDP VBI Data Recovery ............................................................................................................................... 121
7.5 SDP General Setup ........................................................................................................................................ 121
7.5.1 Video Standard Selection (SDP)............................................................................................................... 121
7.5.2 Autodetection of SDP Modes ................................................................................................................... 122
7.5.3 SFL_INV Subcarrier Frequency Lock Inversion (SDP) ........................................................................... 123
7.5.4 Lock Related Controls (SDP) ................................................................................................................... 124
7.6 SDP Color Controls ....................................................................................................................................... 126
ADV7401
7.7 SDP Clamp Operation ................................................................................................................................... 130
7.8 SDP Luma Filter............................................................................................................................................ 132
7.8.1 Y Shaping Filter........................................................................................................................................ 133
7.9 SDP Chroma Filter ........................................................................................................................................ 138
7.10 SDP Gain Operation ...................................................................................................................................... 139
7.10.1 Description........................................................................................................................................... 139
7.10.2 SDP Luma Gain ................................................................................................................................... 141
7.10.3 Chroma Gain........................................................................................................................................ 145
7.11 SDP Chroma Transient Improvement............................................................................................................ 147
7.12 Digital Noise Reduction and Luma Peaking Filter (SDP) ............................................................................. 149
7.13 SDP Comb Filters.......................................................................................................................................... 151
7.13.2 Comb Filter Vertical Blank Control..................................................................................................... 154
7.14 SDP AV Code Insertion and Controls ........................................................................................................... 156
7.15 SDP Synchronization Output Signals ............................................................................................................ 160
7.15.1 HS Configuration ................................................................................................................................. 160
7.15.2 VS and FIELD Configuration .............................................................................................................. 163
7.16 SDP Synchronization Processing................................................................................................................... 179
7.17 SDP VBI Data Decode .................................................................................................................................. 180
7.18 SDP VDP VBI Dataslicer.............................................................................................................................. 180
7.18.1 VDP Default Configuration ................................................................................................................. 180
7.18.2 VDP Ancillary Data Output ................................................................................................................. 184
Table 34: Ancillary Data in Nibble Output Format................................................................................................. 187
7.18.3 I
2
C Interface ......................................................................................................................................... 191
7.18.4 Interrupt Based Reading of I
2
C Registers ............................................................................................ 193
7.18.5 I
2
C Readback Registers........................................................................................................................ 196
7.18.6 CGMS and WSS .................................................................................................................................. 198
7.19 VBI System 2................................................................................................................................................. 204
7.19.1 Gemstar Data Recovery – VBI System 2............................................................................................. 204
7.19.2 Letterbox Detection.............................................................................................................................. 214
7.20 IF Filter Compensation.................................................................................................................................. 216
8 PIXEL PORT CONFIGURATION..................................................................................................................... 218
8.1 SDP Pixel Port Output Modes ....................................................................................................................... 221
8.1.1 LLC1 Output Selection ............................................................................................................................. 221
8.2 CP Pixel Port Output Modes.......................................................................................................................... 222
8.3 CP DDR Output Interface.............................................................................................................................. 223
8.3.1 Pin Assignment......................................................................................................................................... 225
8.3.2 DDR Mode Examples............................................................................................................................... 225
8.4 Default Color Output (CP)............................................................................................................................. 227
8.5 Free Run Mode (CP)...................................................................................................................................... 229
9 SPECIFICATIONS AND CHARACTERISTICS..............................................................................................231
9.1 Electrical Characteristics ............................................................................................................................... 231
9.2 Video Specifications...................................................................................................................................... 233
9.3 Timing Specifications.................................................................................................................................... 234
9.4 Analog Specifications.................................................................................................................................... 235
9.5 Thermal Specifications .................................................................................................................................. 235
9.5.1 Package Thermal Performance ................................................................................................................. 236
9.6 Timing Diagrams........................................................................................................................................... 236
10 MPU PORT DESCRIPTION............................................................................................................................... 238
10.1 Register Access.............................................................................................................................................. 239
10.2 Register Programming................................................................................................................................... 240
10.3 I
2
C Sequencer ................................................................................................................................................ 240
10.4 IP
2
P
C Register Map ........................................................................................................................................... 242
10.5 User Map (IP
2
P
C Register Map Details)............................................................................................................ 250
10.6 IP
2
P
C Interrupt System ...................................................................................................................................... 285
10.6.1 Interrupt Request Output Operation..................................................................................................... 285
10.6.2 Interrupt Drive Level............................................................................................................................ 285
10.6.3 Multiple Interrupt Events ..................................................................................................................... 286
ADV7401
10.6.4 Macrovision Interrupt Selection Bits ................................................................................................... 286
10.7 User Sub Map (IP
2
P
C Interrupt and VDP Register Map) .................................................................................. 287
APPENDIX A.................................................................................................................................................................. 298
External Tuner Configuration ...................................................................................................................................... 298
Programming Setup for ADV7401 External Tuner Mode ........................................................................................... 298
External DVI Rx Input Configuration.......................................................................................................................... 299
Programming Setup for ADV7401 DVI Receiver Mode............................................................................................. 299
External HDMI Rx Input Configuration ...................................................................................................................... 300
Programming Setup for ADV7401 HDMI Receiver Mode ......................................................................................... 300
APPENDIX B.................................................................................................................................................................. 302
IP
2
P
C Programming Examples......................................................................................................................................... 302
CVBS Input on AIN10 - NTSC/PAL/SECAM 8-Bit 422 Output................................................................................ 303
Y/C Input, Y on AIN 11, C on AIN12 - NTSC/PAL/SECAM 8-Bit 422 Output........................................................ 304
CP 525i YPbPr Input, on AIN 6, 5 and 4, 4x1 8-Bit 422 Output................................................................................. 305
CP 525i YPbPr Input on AIN 6, 5 and 4 - 4x1 16-Bit 422 Output (HS and VS timing).............................................. 306
CP 625i YPbPr on AIN 6, 5 and 4 - 4x1 8-Bit 422 Output.......................................................................................... 307
525P YPbPr Input on AIN 6, 5 and 4 - 2x1 16-Bit 422 Output ................................................................................... 307
525P YPbPr Input on AIN 6, 5 and 4 - 2x2 24-Bit 444 RGB Output ......................................................................... 308
525P YPbPr Input on AIN 6, 5 and 4 - 1x1 8-Bit DDR 422 YCrCb Output .............................................................. 309
625P YPbPr Input on AIN 6, 5 and 4 - 2x1 16-Bit 422 Output ................................................................................. 310
625P YPbPr Input on AIN 6, 5 and 4 - 2x2 24-Bit 444 RGB Output .......................................................................... 310
720P YPbPr Input on AIN 6, 5 and 4 - 1x1 24-Bit 444 Output ................................................................................... 311
720P YPbPr Input on AIN 6, 5 and 4 - 1x1 24-Bit 444 RGB Output .......................................................................... 312
720P YPbPr Input on AIN 6, 5 and 4 - 1x1 16-Bit 422 Output ................................................................................... 313
1080i 60Hz 1920x1080 YPbPr Input on AIN 6, 5 and 4 - 24-Bit 444 Output............................................................. 314
1080i 60Hz 1920x1080 YPbPr Input on AIN 6, 5 and 4 - 16-Bit 422 Output............................................................. 314
1080i 60Hz 1920x1080 YPbPr Input on AIN 6, 5 and 4 - 1x1 24-Bit 444 RGB Output............................................. 315
1080i 60Hz 1920x1080 RGB Input Through AIN 1, 2 and 3 - 24-Bit 444 YPbPr Output.......................................... 316
1080i 60Hz 1920x1080 RGB Input Through Graphics Port Output 24-Bit 444 RGB................................................. 317
1080i 50Hz 1920x1080 YPbPr Input 16-Bit 444 YPbPr Output in H and V Mode .................................................... 318
RGB Graphics 640x480 @ 60Hz Autodetecting Sync Source Input 25.125MHz Output........................................... 319
RGB Graphics 640x480 @ 72Hz Autodetecting Sync Source Input 31.5MHz Output............................................... 319
RGB Graphics 640x480 @ 75Hz Autodetecting Sync Source Input 31.5MHz Output............................................... 320
RGB Graphics 640x480 @ 85Hz Autodetecting Sync Source Input 36MHz Output.................................................. 320
RGB Graphics 800x600 @ 56Hz ADV7402 Input 36MHz Output............................................................................. 321
RGB Graphics 800x600 @ 60Hz ADV7402 Input 40MHz Output............................................................................. 321
RGB Graphics 800x600 @ 72Hz ADV7402 Input 50MHz Output............................................................................. 322
RGB Graphics 800x600 @ 75Hz ADV7402 Input 49.5MHz Output.......................................................................... 322
RGB Graphics 800x600 @ 85Hz ADV7402 Input 56.25MHz Output........................................................................ 323
RGB Graphics 1024x768 @ 60Hz ADV7402 Input 65MHz Output........................................................................... 323
RGB Graphics 1024x768 @ 70Hz ADV7402 Input 75MHz Output........................................................................... 324
RGB Graphics 1024x768 @ 75Hz ADV7402 Input 78.75MHz Output......................................................................324
RGB Graphics 1024x768 @ 85Hz ADV7402 Input 94.5MHz Output........................................................................ 325
RGB Graphics 1280x1024 @ 60Hz ADV7402 Input 108MHz Output.......................................................................325
RGB Graphics 1280x1024 @ 75Hz ADV7402 Input 135MHz Output.......................................................................326
YPrPb Input through the SDP – autodetect standard– 10 bit 422 Output .................................................................... 326
Fast Blank Between SD RGB and CVBS Inputs ......................................................................................................... 327
525i/625i SCART RGB IN Input through CP YPbPr 2x1 16-Bit 422 Output.............................................................328
APPENDIX C.................................................................................................................................................................. 330
PCB Layout Recommendations ................................................................................................................................... 330
Analogue Interface Inputs............................................................................................................................................ 330
Power Supply Bypassing ............................................................................................................................................. 330
PLL .............................................................................................................................................................................. 332
Digital Outputs (both Data and Clocks)....................................................................................................................... 332
Digital Inputs ............................................................................................................................................................... 332
Xtal and Load Cap Value Selection ............................................................................................................................. 332
APPENDIX D.................................................................................................................................................................. 334
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