4.3. Resets................................................................................................................51
4.4. Multi Channel DMA...............................................................................................52
4.4.1. Avalon-MM PIO Master..............................................................................52
4.4.2. Avalon-MM Write Master (H2D).................................................................. 53
4.4.3. Avalon-MM Read Master (D2H).................................................................. 54
4.4.4. Avalon-ST Source (H2D)........................................................................... 54
4.4.5. Avalon-ST Sink (D2H)...............................................................................55
4.4.6. User Event MSI-X Interface....................................................................... 56
4.4.7. User Functional Level Reset (FLR) Interface................................................. 56
4.5. Bursting Avalon-MM Master (BAM) Interface............................................................ 57
4.6. Bursting Avalon-MM Slave (BAS) Interface.............................................................. 58
4.7. MSI Interface...................................................................................................... 59
4.8. Config Slave Interface (RP only) ........................................................................... 60
4.9. Hard IP Reconfiguration Interface...........................................................................61
4.10. Config TL Interface.............................................................................................61
4.11. Configuration Intercept Interface (EP Only)........................................................... 62
4.12. Data Mover Interface..........................................................................................62
4.12.1. H2D Data Mover Interface....................................................................... 62
4.12.2. D2H Data Mover Interface....................................................................... 63
4.13. Hard IP Status Interface..................................................................................... 64
5. Parameters (H-Tile)...................................................................................................... 65
5.1. IP Settings..........................................................................................................65
5.1.1. System Settings...................................................................................... 65
5.1.2. MCDMA Settings...................................................................................... 66
5.1.3. Device Identification Registers................................................................... 67
5.1.4. Multifunction and SR-IOV System Settings Parameters [Endpoint Mode].......... 68
5.1.5. Configuration, Debug and Extension Options................................................69
5.1.6. PHY Characteristics.................................................................................. 69
5.1.7. PCI Express / PCI Capabilities Parameters................................................... 70
5.2. Example Designs................................................................................................. 72
6. Parameters (P-Tile) (F-Tile) (R-Tile)............................................................................ 74
6.1. Top-Level Settings............................................................................................... 74
6.2. PCIe0 Settings.................................................................................................... 77
6.2.1. Base Address Register.............................................................................. 77
6.2.2. PCIe0 Configuration, Debug and Extension Options.......................................79
6.2.3. PCIe0 Device Identification Registers.......................................................... 83
6.2.4. PCIe0 PCI Express / PCI Capabilities..........................................................84
6.2.5. MCDMA Settings...................................................................................... 91
6.3. Example Designs................................................................................................. 94
6.4. Analog Parameters (F-Tile MCDMA IP Only)............................................................. 96
6.5. PCIe1 Settings.................................................................................................... 96
6.5.1. PCIe1 Configuration, Debug and Extension Options.......................................97
7. Designing with the IP Core........................................................................................... 98
7.1. Generating the IP Core......................................................................................... 98
7.2. Simulating the IP Core..........................................................................................99
7.3. IP Core Generation Output - Intel Quartus Prime Pro Edition.................................... 100
7.4. Systems Integration and Implementation.............................................................. 103
7.4.1. Required Supporting IP........................................................................... 103
Contents
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Multi Channel DMA Intel
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FPGA IP for PCI Express* User Guide
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