Copyright © 2011 – 2013 ARM. All rights reserved.
ARM DEN0013D (ID012214)
ARM
®
Cortex
™
-A Series
Version: 4.0
Programmer’s Guide
ARM DEN0013D Copyright © 2011 – 2013 ARM. All rights reserved. ii
ID012214 Non-Confidential
ARM Cortex-A Series
Programmer’s Guide
Copyright © 2011 – 2013 ARM. All rights reserved.
Release Information
The following changes have been made to this book.
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Change history
Date Issue Confidentiality Change
25 March 2011 A Non-Confidential First release
10 August 2011 B Non-Confidential Second release. Updated to include Virtualization, Cortex-A15 processor,
and LPAE. Corrected and revised throughout
25 June 2012 C Non-Confidential Updated to include Cortex-A7 processor, and big.LITTLE. Index added.
Corrected and revised throughout.
22 January 2014 D Non-Confidential Updated to include Cortex-A12 processor, Cache Coherent Interconnect,
expanded GIC coverage, Multi-core processors, Corrected and revised
throughout.
ARM DEN0013D Copyright © 2011 – 2013 ARM. All rights reserved. iii
ID012214 Non-Confidential
Contents
ARM Cortex-A Series Programmer’s Guide
Preface
Preface to the 4th Edition ................................................................................................ ix
Glossary ............................................................................................................................ x
Typographical conventions ............................................................................................ xiv
Feedback on this book .................................................................................................... xv
References .................................................................................................................... xvi
Chapter 1 Introduction
1.1 History ........................................................................................................................... 1-2
1.2 System-on-Chip (SoC) .................................................................................................. 1-4
1.3 Embedded systems ...................................................................................................... 1-5
Chapter 2 ARM Architecture and Processors
2.1 Architectural profiles ..................................................................................................... 2-2
2.2 Architecture history and extensions .............................................................................. 2-3
2.3 Processor properties ..................................................................................................... 2-8
2.4 Cortex-A series processors ........................................................................................ 2-10
2.5 Key architectural points of ARM Cortex-A series processors ..................................... 2-16
Chapter 3 ARM Processor Modes and Registers
3.1 Registers ....................................................................................................................... 3-6
Chapter 4 Introduction to Assembly Language
4.1 Comparison with other assembly languages ................................................................ 4-2
4.2 The ARM instruction sets .............................................................................................. 4-3
4.3 Introduction to the GNU Assembler .............................................................................. 4-5
4.4 ARM tools assembly language ..................................................................................... 4-9
4.5 Interworking ................................................................................................................ 4-11
Contents
ARM DEN0013D Copyright © 2011 – 2013 ARM. All rights reserved. iv
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4.6 Identifying assembly code .......................................................................................... 4-12
4.7 Compatibility with ARMv8-A ....................................................................................... 4-13
Chapter 5 ARM/Thumb Unified Assembly Language Instructions
5.1 Instruction set basics .................................................................................................... 5-2
5.2 Data processing operations .......................................................................................... 5-6
5.3 Memory instructions .................................................................................................... 5-13
5.4 Branches ..................................................................................................................... 5-15
5.5 Saturating arithmetic ................................................................................................... 5-16
5.6 Miscellaneous instructions .......................................................................................... 5-17
Chapter 6 Floating-Point
6.1 Floating-point basics and the IEEE-754 standard ........................................................ 6-2
6.2 VFP support in GCC ..................................................................................................... 6-8
6.3 VFP support in the ARM Compiler ................................................................................ 6-9
6.4 VFP support in Linux .................................................................................................. 6-10
6.5 Floating-point optimization .......................................................................................... 6-11
Chapter 7 Introducing NEON
7.1 SIMD ............................................................................................................................. 7-2
7.2 NEON architecture overview ........................................................................................ 7-5
7.3 NEON C Compiler and assembler .............................................................................. 7-11
Chapter 8 Caches
8.1 Why do caches help? ................................................................................................... 8-3
8.2 Cache drawbacks ......................................................................................................... 8-4
8.3 Memory hierarchy ......................................................................................................... 8-5
8.4 Cache architecture ........................................................................................................ 8-6
8.5 Cache policies ............................................................................................................ 8-13
8.6 Write and Fetch buffers .............................................................................................. 8-15
8.7 Cache performance and hit rate ................................................................................. 8-16
8.8 Invalidating and cleaning cache memory .................................................................... 8-17
8.9 Point of coherency and unification .............................................................................. 8-19
8.10 Level 2 cache controller .............................................................................................. 8-22
8.11 Parity and ECC in caches ........................................................................................... 8-23
Chapter 9 The Memory Management Unit
9.1 Virtual memory .............................................................................................................. 9-3
9.2 The Translation Lookaside Buffer ................................................................................. 9-4
9.3 Choice of page sizes .................................................................................................... 9-6
9.4 First level address translation ....................................................................................... 9-7
9.5 Level 2 translation tables ............................................................................................ 9-11
9.6 Memory attributes ....................................................................................................... 9-14
9.7 Multi-tasking and OS usage of translation tables ....................................................... 9-17
Chapter 10 Memory Ordering
10.1 ARM memory ordering model ..................................................................................... 10-3
10.2 Memory barriers .......................................................................................................... 10-6
10.3 Cache coherency implications .................................................................................. 10-11
Chapter 11 Exception Handling
11.1 Types of exception ...................................................................................................... 11-3
11.1.1 Exception priorities ..................................................................................................... 11-6
11.2 Exception handling ................................................................................................... 11-10
11.3 Other exception handlers .......................................................................................... 11-12
11.4 Linux exception program flow ................................................................................... 11-14
Contents
ARM DEN0013D Copyright © 2011 – 2013 ARM. All rights reserved. v
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Chapter 12 Interrupt Handling
12.1 External interrupt requests .......................................................................................... 12-2
12.2 The Generic Interrupt Controller ................................................................................. 12-7
Chapter 13 Boot Code
13.1 Booting a bare-metal system ...................................................................................... 13-2
13.2 Configuration .............................................................................................................. 13-6
13.3 Booting Linux .............................................................................................................. 13-7
Chapter 14 Porting
14.1 Endianness ................................................................................................................. 14-2
14.2 Alignment .................................................................................................................... 14-5
14.3 Miscellaneous C porting issues .................................................................................. 14-7
14.4 Porting ARM assembly code to ARMv7-A ................................................................ 14-10
14.5 Porting ARM code to Thumb .................................................................................... 14-11
Chapter 15 Application Binary Interfaces
15.1 Procedure Call Standard ............................................................................................ 15-2
15.2 Mixing C and assembly code ...................................................................................... 15-8
Chapter 16 Profiling
16.1 Profiler output ............................................................................................................. 16-3
Chapter 17 Optimizing Code to Run on ARM Processors
17.1 Compiler optimizations ............................................................................................... 17-2
17.2 ARM memory system optimization ............................................................................. 17-7
17.3 Source code modifications ........................................................................................ 17-12
Chapter 18 Multi-core processors
18.1 Multi-processing ARM systems .................................................................................. 18-3
18.2 Symmetric multi-processing ........................................................................................ 18-5
18.3 Asymmetric multi-processing ...................................................................................... 18-7
18.4 Heterogeneous multi-processing ................................................................................ 18-8
18.5 Cache coherency ........................................................................................................ 18-9
18.6 TLB and cache maintenance broadcast ................................................................... 18-13
18.7 Handling interrupts in an SMP system ...................................................................... 18-14
18.8 Exclusive accesses ................................................................................................... 18-15
18.9 Booting SMP systems ............................................................................................... 18-17
18.10 Private memory region .............................................................................................. 18-19
Chapter 19 Parallelizing Software
19.1 Amdahl’s law ............................................................................................................... 19-2
19.2 Decomposition methods ............................................................................................. 19-3
19.3 Threading models ....................................................................................................... 19-5
19.4 Threading libraries ...................................................................................................... 19-6
19.5 Performance issues .................................................................................................... 19-9
19.6 Synchronization mechanisms in the Linux kernel ..................................................... 19-11
19.7 Profiling in SMP systems .......................................................................................... 19-13
Chapter 20 Power Management
20.1 Idle management ........................................................................................................ 20-3
20.2 Hotplug ....................................................................................................................... 20-6
20.3 Dynamic Voltage and Frequency Scaling ................................................................... 20-7
20.4 Assembly language power instructions ...................................................................... 20-8
20.5 Power State Coordination Interface ............................................................................ 20-9
Chapter 21 Security
21.1 TrustZone hardware architecture ................................................................................ 21-2