################################################################################
# Vivado (TM) v2019.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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FPGA实现SD卡控制器
共1361个文件
xml:230个
v:214个
vhdl:139个
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2023-08-22
23:16:44
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介绍SD卡及如何使用的文章有很多,这里不再赘述,这里给大家推荐几个相关的文章都介绍的比较详细;本文重点介绍如何在SPI模式下使用SD卡,包括初始化的步骤,读写数据的操作步骤及SD卡的响应内容等,最后附上完整的工程文件及简单的仿真(模拟SD卡的.v文件目前只能够响应命令,对写入数据后的响应没有涉及,可以直接上板观察具体响应) SD2.0协议详解:命令格式、初始化/读取/写入 基于FPGA的SD卡的数据读写实现(SD NAND FLASH) SD卡的使用过程如下: SD卡初始化—— SD卡写数据(单个数据块)—— SD卡读数据(单个数据块) rtl文件夹中一共有6个.v文件,从上至下分别代表初始化时钟生成、模式选择、初始化、SD卡、SD卡写以及顶层文件。各部分介绍如下: clk_init_gen:用于生成初始化需要的时钟; mode_sel:表示目前的工作模式为初始化、SD卡写还是SD卡读; sd_init:完成SD卡的初始化; sd_read:完成SD卡的读功能; sd_write:完成SD卡的写功能 SD_top的这一部分为产生写数据,然后存入到sd_write模块的fifo中,
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FPGA实现SD卡控制器 (1361个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
_info 19KB
_info 9KB
_info 6KB
_info 5KB
_info 143B
_info 143B
_lock 0B
_vmake 29B
_vmake 29B
_vmake 29B
_vmake 29B
xsim.ini.bak 26KB
elaborate.bat 1KB
compile.bat 992B
simulate.bat 918B
simulate.bat 815B
compile.bat 809B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
sd_top.bit 10.91MB
xsim_1.c 33KB
xsim.dbg 45KB
sd_top_routed.dcp 9.84MB
sd_top_placed.dcp 8.23MB
sd_top_physopt.dcp 8.21MB
sd_top_opt.dcp 6.66MB
u_ila_0.dcp 4.68MB
u_ila_0.dcp 4.39MB
u_ila_0.dcp 4.17MB
u_ila_0.dcp 3.96MB
u_ila_0.dcp 3.87MB
u_ila_0.dcp 3.79MB
u_ila_0.dcp 3.77MB
u_ila_0.dcp 3.76MB
u_ila_0.dcp 3.76MB
u_ila_0.dcp 3.71MB
u_ila_0.dcp 3.64MB
u_ila_0.dcp 3.36MB
u_ila_0.dcp 3.35MB
u_ila_0.dcp 3.28MB
u_ila_0.dcp 2.85MB
u_ila_1.dcp 2.85MB
u_ila_0.dcp 2.79MB
u_ila_0.dcp 2.61MB
u_ila_1.dcp 2.59MB
u_ila_0.dcp 2.28MB
u_ila_0.dcp 1.84MB
u_ila_0.dcp 1.8MB
u_ila_0.dcp 1.78MB
u_ila_0.dcp 1.74MB
u_ila_0.dcp 1.74MB
u_ila_0.dcp 1.74MB
u_ila_0.dcp 1.71MB
u_ila_0.dcp 1.68MB
u_ila_0.dcp 1.66MB
u_ila_0.dcp 1.65MB
u_ila_0.dcp 1.58MB
u_ila_0.dcp 1.51MB
u_ila_0.dcp 1.5MB
u_ila_0.dcp 1.48MB
u_ila_0.dcp 1.45MB
u_ila_0.dcp 1.4MB
u_ila_0.dcp 1.4MB
u_ila_0.dcp 1.36MB
u_ila_0.dcp 1.36MB
u_ila_0.dcp 1.16MB
u_ila_0.dcp 1.11MB
u_ila_0.dcp 870KB
u_ila_0.dcp 842KB
u_ila_1.dcp 823KB
u_ila_1.dcp 766KB
u_ila_1.dcp 727KB
u_ila_1.dcp 577KB
u_ila_1.dcp 565KB
dbg_hub.dcp 369KB
dbg_hub.dcp 360KB
dbg_hub.dcp 350KB
sd_top.dcp 222KB
wr_data_fifo.dcp 157KB
wr_data_fifo.dcp 156KB
fifo_generator_0.dcp 156KB
wr_data_fifo.dcp 136KB
wr_data_fifo.dcp 136KB
wr_data_fifo.dcp 126KB
wr_data_fifo.dcp 126KB
wr_data_fifo.dcp 125KB
vio_0.dcp 117KB
vio_0.dcp 117KB
vio_0.dcp 117KB
vio_0.dcp 112KB
vio_0.dcp 111KB
fifo_generator_0.dcp 98KB
wr_data_fifo.dcp 97KB
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