efinity-2023.1.150.5.11-windows-x64-patch.zip

Last updated: June 23, 2023 *** Errata *** *** Upgrading from previous Efinity versions *** Previously generated data files from Efinity compilations (such as old synthesis, place and route output files) may not be compatible with this version of Efinity software. Full recompilation is recommended. NOTE #1: [Trion] Full recompilation in Efinity 2023.1 is required. Old compilation results will not function in placement and routing. NOTE #2: [Titanium] HVIO output buffer timing values are updated in this release. *** Description *** This is a release package of the Efinity tools for compiling and simulating designs targeting the Efinix programmable logic devices. *** New features in Efinity 2023.1 *** -- [Trion] Adds T20Q100F3, T13Q100F3 devices, with in-package flash memory. [DEVINFRA-719] -- Adds Netlist Viewer (beta) feature to visualize elaborated design logic. [NV-105] -- Adds various improvements for SDC timing constraints parsing: - Adds support for multiple SDC constraint files [VPR-984] - -add option support for set_input_delay, set_output_delay, create_clock [VPR-1532] -- Adds BRAM Update tool to quickly update BRAM initial contents in bitstreams, without requiring rerun of synthesis, placement, or routing. [SYN-631] -- Adds support for 'syn_keep' directives to logic synthesis tool. [SYN-654] -- Upgrades bundled Python tool to version 3.11 [DEVINFRA-723] * New Efinity support for Titanium family * -- [Titanium] Adds Beneficial Clock Skew optimization to place and route tool, on by default. Existing designs may see significant fmax improvement using this feature. [TROUTE-386, VPR-1774] -- [Titanium] Adds general improvements to place and route quality of results. -- [Titanium] Adds carry-skip adder physical optimization. [SYN-658] -- [Titanium] Adds Spread Spectrum (SSC) PLL to Interface Designer for some Ti180, Ti120, Ti90 devices. [PT-1724] -- [Titanium] Improves SPI_FLASH Interface Designer support for Ti60F100S3F2, Ti35F100S3F2 in-package flash memory [PT-1829] *** Fixed issues in Efinity 2023.1 *** Note: this list is not comprehensive -- [Titanium] Fixes an overly strict True Dual Port BRAM WRITE_FIRST check that may produce an illegal write-mode [DEVINFRA-769] -- Fixes synthesis crash during bit-blasting of incompatible BRAM configurations [SYN-701, SYN-710, SYN-708] -- Fixes handling of inout port in submodule with same signal connection triggering incorrect trimming [SYN-709] -- Improves some error messages in the programmer when USB drivers are not found [PROG-444] -- [Titanium] Improves router messages when clock pairs lead to difficult hold requirements. (Consider assigning unrelated clocks into exclusive clock groups in SDC constraints in these scenarios.) [VPR-1785] -- [Titanium] Fixes several issues in general router handling of difficult hold requirements [VPR-1772] -- Improves handling of VHDL case insensitivity and suffixes [SYN-698] -- Fixes synthesis bug in sub-expression optimization [SYN-695] -- [Titanium] Fixes incorrect DSP utilization reporting in synthesis report file [SYN-693] -- Fixes synthesis bug with control logic discovery after large memory decomposition for True Dual Port BRAM [SYN-681] -- Fixes synthesis error using syn_ramstyle directive [SYN-677] *** Contents *** arch/ : Architecture description files bin/ : Executable binaries for synthesis, place & route, etc. debugger/ : Hardware Debugger Python libraries doc/ : Documentation ipm/ : IP Manager Python libraries lib/ : Dynamic libraries log/ : GUI output logs pgm/ : Programmer Python libraries project/ : Example projects python311/ : Python installation (Windows only) pt/ : Interface Designer Python libraries scripts/ : Helper scripts for running different FPGA flows sim_models/ : Functional simulation models for Efinity primitives security/ : Tools for bitstream security tcl_packages/ : Tcl library files, init scripts license*.txt : License files readme.txt : This file *** Setup Requirements *** This release has been verified to run on several mainstream 64-bit desktop Linux distributions. Efinix recommends Ubuntu 18.04 x86-64 (or later versions) or Red Hat Enterprise / CentOS 7.4 x86-64 (or later versions). The Efinity software is also supported for Microsoft Windows 10 64-bit (or more recent versions). Linux Requirements: -- 64-bit OS installed -- The Efinity GUI tool requires X11 installed. Windows Requirements: -- 64-bit OS installed -- MSVC 2019 x64 runtime distributable installed. This can be freely downloaded and installed from https://docs.microsoft.com/en-us/cpp/windows/latest-supported-vc-redist?view=msvc-170 Hardware Recommendations: -- x86-64 processor, at least dual-core -- machine memory requirements may vary depending on the size of Efinix device and customer design --------------------------------------------------------------- FAMILY DEVICE Minimum memory recommendation --------------------------------------------------------------- Trion T4/T8/T13/T20/T35 16 GB Trion T55/T85/T120 32 GB Titanium Ti35/Ti60 16 GB Titanium Ti90/Ti120/Ti180 32 GB --------------------------------------------------------------- *** Third Party Simulator *** The Efinity tools do not include third party simulators, nor any explicit tool integration with third party simulators. However, three different simulators have been verified to work with Efinity-generated Verilog netlist files: -- Incisive Enterprise Simulator (R). Incisive has robust Verilog HDL language support as well as excellent simulation runtime. See Cadence documentation for details. -- QuestaSim (R). QuestaSim has robust Verilog HDL language support as well as the best simulation runtime. See Mentor Graphics documentation for details. -- iVerilog. For small designs or prototyping, this free open-source utility may fit your needs. iVerilog is available in Ubuntu, CentOS, and other Linux repositories, or freely downloadable from the web. Windows versions can be downloaded from http://bleyer.org/icarus/ To simulate a post-synthesis (or later compiler stage) Verilog HDL netlist produced by the Efinity tools, please include the following library path as a resource in your third party simulator: <Efinity top-level path>/sim_models/verilog *** Installation *** Linux installation: Simply unzip/untar the efinity package into a suitable user directory. > tar -xjvf efinity-<version>.tar.bz2 Optional installation: To use the Efinity programmer, you need to install the included USB UDEV device manager. (i.e., /etc/udev/rules.d/...) Run the following command with root privilege: > sudo ./bin/install_usb_driver.sh You can run the following script to install a shortcut in your Desktop directory. (i.e., ~/Desktop) > ./bin/install_desktop.sh Windows installation: Double-click on the efinity-<version>.msi installer package and follow the on-screen instructions. Optional installation: To use the Efinity programmer, you need to install the appropriate USB drivers. Efinix recommends using the Zadig software for this purpose. 1. Download and install the Zadig software (version 2.7 or later) from zadig.akeo.ie. 2. Open the Zadig s