BusMatrix Verilog COde配置生成源代码

#- --===============================================================-- #- This confidential and proprietary software may be used only as #- authorised by a licensing agreement from ARM Limited #- (C) COPYRIGHT 2001-2007 ARM Limited #- ALL RIGHTS RESERVED #- The entire notice above must be reproduced on all authorised #- copies and copies may only be made to the extent permitted #- by a licensing agreement from ARM Limited. #- ------------------------------------------------------------------- #- #- Version and Release Control Information: #- #- File Name : README.txt,v #- File Revision : 1.1 #- #- Release Information : BP010-AC-30009-r3p0-00rel3 #- #- ------------------------------------------------------------------- #- Purpose : BusMatrix verilog/rtl_source README file #- #- --===============================================================-- This directory contains the Verilog source of the 2x3 BusMatrix component used in the EASY_ML example system. Similar to all ADK components, this directory is the location where the RTL of the BusMatrix is used in compilation and synthesis. So to use the EASY_ML example system, make sure the original 2x3 BusMatrix RTL is in this directory. If you want to compile or synthesize another BusMatrix configuration, copy the generated RTL to this directory (normally the RTL is copied from verilog/built directory). ======================== End of README.txt ===========================