© 2008 Microchip Technology Inc. Preliminary DS39662C
ENC28J60
Data Sheet
Stand-Alone Ethernet Controller
with SPI Interface
DS39662C-page ii Preliminary © 2008 Microchip Technology Inc.
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© 2008 Microchip Technology Inc. Preliminary DS39662C-page 1
ENC28J60
Ethernet Controller Features
• IEEE 802.3™ Compatible Ethernet Controller
• Fully Compatible with 10/100/1000Base-T Networks
• Integrated MAC and 10Base-T PHY
• Supports One 10Base-T Port with Automatic
Polarity Detection and Correction
• Supports Full and Half-Duplex modes
• Programmable Automatic Retransmit on Collision
• Programmable Padding and CRC Generation
• Programmable Automatic Rejection of Erroneous
Packets
• SPI Interface with Clock Speeds Up to 20 MHz
Buffer
• 8-Kbyte Transmit/Receive Packet Dual Port SRAM
• Configurable Transmit/Receive Buffer Size
• Hardware Managed Circular Receive FIFO
• Byte-Wide Random and Sequential Access with
Auto-Increment
• Internal DMA for Fast Data Movement
• Hardware Assisted Checksum Calculation for
Various Network Protocols
Medium Access Controller (MAC)
Features
• Supports Unicast, Multicast and Broadcast
Packets
• Programmable Receive Packet Filtering and Wake-up
Host on Logical AND or OR of the Following:
- Unicast destination address
- Multicast address
- Broadcast address
- Magic Packet™
- Group destination addresses as defined by
64-bit Hash Table
- Programmable Pattern Matching of up to
64 bytes at user-defined offset
Physical Layer (PHY) Features
• Loopback mode
• Two Programmable LED Outputs for LINK, TX,
RX, Collision and Full/Half-Duplex Status
Operational
• Six Interrupt Sources and One Interrupt Output Pin
• 25 MHz Clock Input Requirement
• Clock Out Pin with Programmable Prescaler
• Operating Voltage of 3.1V to 3.6V (3.3V typical)
• 5V Tolerant Inputs
• Temperature Range: -40°C to +85°C Industrial,
0°C to +70°C Commercial (SSOP only)
• 28-Pin SPDIP, SSOP, SOIC, QFN Packages
Package Types
ENC28J60
28-Pin SPDIP, SSOP, SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
OSC2
OSC1
LEDA
LEDB
TPIN+
TPIN-
INT
NC*
1
2
3
4
5
6
7
8910
28 27 26 25 24 23 22
21
20
19
ENC28J60
11 12 13 14
18
17
16
15
VDDOSC
VDDTX
TPOUT+
TPOUT-
28-pin QFN
RESET
CS
SO
SI
SCK
RBIAS
VSSRX
CLKOUT
VCAP
VDDRX
VSSOSC
VDDPLL
VSSPLL
VSSTX
VDD
VSS
VCAP
OSC2
OSC1
V
DDRX
VSSTX
TPOUT+
TPOUT-
LEDA
LEDB
V
DDOSC
VSSOSC
VDDTX
VDDPLL
VSSPLL
CLKOUT
RESET
CS
SO
SI
TPIN+
TPIN-
RBIAS
INT
NC*
SCK
V
DD
VSS
VSSRX
* Reserved pin; always leave disconnected.
Stand-Alone Ethernet Controller with SPI Interface
ENC28J60
DS39662C-page 2 Preliminary © 2008 Microchip Technology Inc.
Table of Contents
1.0 Overview ...................................................................................................................................................................................... 3
2.0 External Connections ................................................................................................................................................................... 5
3.0 Memory Organization ................................................................................................................................................................. 11
4.0 Serial Peripheral Interface (SPI)................................................................................................................................................. 25
5.0 Ethernet Overview...................................................................................................................................................................... 31
6.0 Initialization................................................................................................................................................................................. 33
7.0 Transmitting and Receiving Packets .......................................................................................................................................... 39
8.0 Receive Filters............................................................................................................................................................................ 47
9.0 Duplex Mode Configuration and Negotiation.............................................................................................................................. 53
10.0 Flow Control ............................................................................................................................................................................... 55
11.0 Reset .......................................................................................................................................................................................... 59
12.0 Interrupts .................................................................................................................................................................................... 63
13.0 Direct Memory Access Controller............................................................................................................................................... 71
14.0 Power-Down............................................................................................................................................................................... 73
15.0 Built-in Self-Test Controller ........................................................................................................................................................ 75
16.0 Electrical Characteristics ............................................................................................................................................................ 79
17.0 Packaging Information................................................................................................................................................................ 83
Appendix A: Revision History............................................................................................................................................................... 89
The Microchip Web Site....................................................................................................................................................................... 91
Customer Change Notification Service ................................................................................................................................................ 91
Customer Support ................................................................................................................................................................................ 91
Reader Response ................................................................................................................................................................................ 92
Index .................................................................................................................................................................................................... 93
Product Identification System............................................................................................................................................................... 95
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© 2008 Microchip Technology Inc. Preliminary DS39662C-page 3
ENC28J60
1.0 OVERVIEW
The ENC28J60 is a stand-alone Ethernet controller
with an industry standard Serial Peripheral Interface
(SPI). It is designed to serve as an Ethernet network
interface for any controller equipped with SPI.
The ENC28J60 meets all of the IEEE 802.3 specifica-
tions. It incorporates a number of packet filtering
schemes to limit incoming packets. It also provides an
internal DMA module for fast data throughput and hard-
ware assisted checksum calculation, which is used in
various network protocols. Communication with the
host controller is implemented via an interrupt pin and
the SPI, with clock rates of up to 20 MHz. Two
dedicated pins are used for LED link and network
activity indication.
A simple block diagram of the ENC28J60 is shown in
Figure 1-1. A typical application circuit using the device
is shown in Figure 1-2. With the ENC28J60, two pulse
transformers and a few passive components are all that
are required to connect a microcontroller to an Ethernet
network.
The ENC28J60 consists of seven major functional
blocks:
1. An SPI interface that serves as a communica-
tion channel between the host controller and the
ENC28J60.
2. Control registers which are used to control and
monitor the ENC28J60.
3. A dual port RAM buffer for received and
transmitted data packets.
4. An arbiter to control the access to the RAM
buffer when requests are made from DMA,
transmit and receive blocks.
5. The bus interface that interprets data and
commands received via the SPI interface.
6. The MAC (Medium Access Control) module that
implements IEEE 802.3 compliant MAC logic.
7. The PHY (Physical Layer) module that encodes
and decodes the analog data that is present on
the twisted-pair interface.
The device also contains other support blocks, such as
the oscillator, on-chip voltage regulator, level translators
to provide 5V tolerant I/Os and system control logic.
FIGURE 1-1: ENC28J60 BLOCK DIAGRAM
Dual Port RAM
8 Kbytes
DMA &
Checksum
TXBM
RXBM
Arbiter
Flow Control
Host Interface
Control
Registers
25 MHz
Power-on
PHY
Bus Interface
SPI
MII
Interface
MIIM
Interface
TPOUT+
TPOUT-
TPIN+
TPIN-
TX
RX
RBIAS
OSC1
OSC2
Voltage
System Control
CS
(1)
SI
(1)
SO
SCK
(1)
INT
VCAP
CLKOUT
LEDA
LEDB
RESET
(1)
RXF (Filter)
RX
TX
MAC
ch0
ch1
ch0
ch1
Buffer
Note 1: These pins are 5V tolerant.
Regulator
Reset
Oscillator
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