LATTICE-ECP3-datasheet_vlt2900变频器说明书下载资源-CSDN文库

需积分: 9 5 浏览量 2019-03-01 21:29:44 上传评论收藏 2.64MB PDF 举报

莱迪斯ECP3器件系列数据手册涵盖了关于该系列FPGA芯片的详细技术规格和性能参数。根据手册提供的信息，我们可以了解到莱迪斯ECP3系列FPGA具备的一些关键技术特点和功能。莱迪斯ECP3系列FPGA具有较高的逻辑密度，提供了17K到149K的查找表(LUTs)数量，这使得该系列FPGA能够满足对系统集成度要求越来越高的应用需求。此外，ECP3系列提供了116到586个可配置的I/O引脚数量，为设计人员提供了灵活的接口配置选项。 ECP3系列FPGA的一个突出特点是集成了串行器/解串器（SERDES），支持高达3.2Gbps的速率，适用于多种数据传输协议，包括PCI Express、SONET/SDH、以太网（1GbE、SGMII、XAUI）、CPRI、SMPTE3G和Serial RapidIO等。每个设备最多支持16个通道，这为高速数据传输提供了强大的支持。在数字信号处理方面，ECP3系列使用了sysDSP™技术，通过全可级联的切片架构实现高性能的乘加运算。每一片切片支持半36x36、两个18x18或四个9x9乘法器，还包括更高级的18x36乘法器和18x18乘累加器（MAC）操作。这些特点为需要进行复杂算法运算的应用提供了高效的数据处理能力。在存储资源方面，ECP3系列FPGA集成了高达6.85Mbit的sysMEM™嵌入式块RAM（EBR）和36K到303K位的分布式RAM，能够满足不同应用对存储需求的多样性。时钟管理方面，ECP3系列FPGA内建了sysCLOCK技术，包括两个延迟锁环（DLLs）和最多十个相位锁定环（PLLs）。这些硬件时钟管理单元能够提供灵活的时钟方案，支持高速时钟域之间的转换。为了支持源同步I/O，ECP3系列FPGA提供了专用的读写均衡功能、专用的齿轮逻辑，并支持多种源同步标准，如ADC/DAC、7:1LVDS、XGMII等。同时，该系列FPGA还支持高速ADC/DAC设备，以及支持DDR/DDR2/DDR3内存的专用读写均衡功能和可选的符号间干扰（ISI）修正。在I/O支持方面，ECP3系列FPGA提供了可编程的sysI/O™缓冲器，支持广泛的接口标准，包括LVTTL、LVCMOS、SSTL、HSTL、PCI、LVDS、Bus-LVDS等。这些I/O缓冲器还支持片上终端和可选的输入均衡滤波器，为不同的接口标准提供了优化的支持。莱迪斯ECP3系列FPGA提供了多种封装选项，包括328csBGA（10x10mm）、256ftBGA（17x17mm）、484fpBGA（23x23mm）、672fpBGA（27x27mm）和1156fpBGA（35x35mm）。这些封装提供了不同数量的SERDES通道和I/O组合，以适应不同应用的特定需求。莱迪斯ECP3系列FPGA提供了丰富的功能和特性，使其成为设计高性能、低功耗系统时的理想选择。这些FPGA特别适用于通信、计算和工业自动化等领域的应用。

资源推荐

资源详情

资源评论

LatticeECP3 Family Data Sheet

DS1021 Version 02.0EA, November 2011

www.latticesemi.com 1-1 DS1021 Introduction_01.5

November 2011 Data Sheet DS1021

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Features

 Higher Logic Density for Increased System

Integration

• 17K to 149K LUTs

• 116 to 586 I/Os

 Embedded SERDES

• 150 Mbps to 3.2 Gbps for Generic 8b10b, 10-bit

SERDES, and 8-bit SERDES modes

• Data Rates 230 Mbps to 3.2 Gbps per channel

for all other protocols

• Up to 16 channels per device: PCI Express,

SONET/SDH, Ethernet (1GbE, SGMII, XAUI),

CPRI, SMPTE 3G and Serial RapidIO

 sysDSP™

• Fully cascadable slice architecture

• 12 to 160 slices for high performance multiply

and accumulate

• Powerful 54-bit ALU operations

• Time Division Multiplexing MAC Sharing

• Rounding and truncation

• Each slice supports

– Half 36x36, two 18x18 or four 9x9 multipliers

– Advanced 18x36 MAC and 18x18 Multiply-

Multiply-Accumulate (MMAC) operations

 Flexible Memory Resources

• Up to 6.85Mbits sysMEM™ Embedded Block

RAM (EBR)

• 36K to 303K bits distributed RAM

 sysCLOCK Analog PLLs and DLLs

• Two DLLs and up to ten PLLs per device

 Pre-Engineered Source Synchronous I/O

• DDR registers in I/O cells

• Dedicated read/write levelling functionality

• Dedicated gearing logic

• Source synchronous standards support

– ADC/DAC, 7:1 LVDS, XGMII

– High Speed ADC/DAC devices

• Dedicated DDR/DDR2/DDR3 memory with DQS

support

• Optional Inter-Symbol Interference (ISI) 

correction on outputs

 Programmable sysI/O™ Buffer Supports

Wide Range of Interfaces

• On-chip termination

• Optional equalization filter on inputs

• LVTTL and LVCMOS 33/25/18/15/12

• SSTL 33/25/18/15 I, II

• HSTL15 I and HSTL18 I, II

• PCI and Differential HSTL, SSTL

• LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS

 Flexible Device Configuration

• Dedicated bank for configuration I/Os

• SPI boot flash interface

• Dual-boot images supported

• Slave SPI

• TransFR™ I/O for simple field updates

• Soft Error Detect embedded macro

 System Level Support

• IEEE 1149.1 and IEEE 1532 compliant

• Reveal Logic Analyzer

• ORCAstra FPGA configuration utility

• On-chip oscillator for initialization & general use

• 1.2V core power supply

Table 1-1. LatticeECP3™ Family Selection Guide

Device ECP3-17 ECP3-35 ECP3-70 ECP3-95 ECP3-150

LUTs (K) 17336792149

sysMEM Blocks (18Kbits) 38 72 240 240 372

Embedded Memory (Kbits) 700 1327 4420 4420 6850

Distributed RAM Bits (Kbits) 36 68 145 188 303

18X18 Multipliers 24 64 128 128 320

SERDES (Quad) 11334

PLLs/DLLs 2 / 2 4 / 2 10 / 2 10 / 2 10 / 2

Packages and SERDES Channels/ I/O Combinations

328 csBGA (10x10 mm) 2 / 116

256 ftBGA (17x17 mm) 4 / 133 4 / 133

484 fpBGA (23x23 mm) 4 / 222 4 / 295 4 / 295 4 / 295

672 fpBGA (27x27 mm) 4 / 310 8 / 380 8 / 380 8 / 380

1156 fpBGA (35x35 mm) 12 / 490 12 / 490 16 / 586

LatticeECP3 Family Data Sheet

Introduction

1-2

Introduction

Lattice Semiconductor LatticeECP3 Family Data Sheet

Introduction

The LatticeECP3™ (EConomy Plus Third generation) family of FPGA devices is optimized to deliver high perfor-

mance features such as an enhanced DSP architecture, high speed SERDES and high speed source synchronous

interfaces in an economical FPGA fabric. This combination is achieved through advances in device architecture

and the use of 65nm technology making the devices suitable for high-volume, high-speed, low-cost applications.

The LatticeECP3 device family expands look-up-table (LUT) capacity to 149K logic elements and supports up to

586 user I/Os. The LatticeECP3 device family also offers up to 320 18x18 multipliers and a wide range of parallel

I/O standards.

The LatticeECP3 FPGA fabric is optimized with high performance and low cost in mind. The LatticeECP3 devices

utilize reconfigurable SRAM logic technology and provide popular building blocks such as LUT-based logic, distrib-

uted and embedded memory, Phase Locked Loops (PLLs), Delay Locked Loops (DLLs), pre-engineered source

synchronous I/O support, enhanced sysDSP slices and advanced configuration support, including encryption and

dual-boot capabilities.

The pre-engineered source synchronous logic implemented in the LatticeECP3 device family supports a broad

range of interface standards, including DDR3, XGMII and 7:1 LVDS.

The LatticeECP3 device family also features high speed SERDES with dedicated PCS functions. High jitter toler-

ance and low transmit jitter allow the SERDES plus PCS blocks to be configured to support an array of popular

data protocols including PCI Express, SMPTE, Ethernet (XAUI, GbE, and SGMII) and CPRI. Transmit Pre-empha-

sis and Receive Equalization settings make the SERDES suitable for transmission and reception over various

forms of media.

The LatticeECP3 devices also provide flexible, reliable and secure configuration options, such as dual-boot capa-

bility, bit-stream encryption, and TransFR field upgrade features.

The Lattice Diamond™ and ispLEVER

design software allows large complex designs to be efficiently imple-

mented using the LatticeECP3 FPGA family. Synthesis library support for LatticeECP3 is available for popular logic

synthesis tools. Diamond and ispLEVER tools use the synthesis tool output along with the constraints from its floor

planning tools to place and route the design in the LatticeECP3 device. The tools extract the timing from the routing

and back-annotate it into the design for timing verification.

Lattice provides many pre-engineered IP (Intellectual Property) modules for the LatticeECP3 family. By using these

configurable soft core IPs as standardized blocks, designers are free to concentrate on the unique aspects of their

design, increasing their productivity.

www.latticesemi.com 2-1 DS1021 Architecture_01.8

November 2011 Data Sheet DS1021

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Architecture Overview

Each LatticeECP3 device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Inter-

spersed between the rows of logic blocks are rows of sysMEM™ Embedded Block RAM (EBR) and rows of sys-

DSP™ Digital Signal Processing slices, as shown in Figure 2-1. The LatticeECP3-150 has four rows of DSP slices;

all other LatticeECP3 devices have two rows of DSP slices. In addition, the LatticeECP3 family contains SERDES

Quads on the bottom of the device.

There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional Unit

without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM and ROM functions. The PFF

block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks are optimized for

flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a two-

dimensional array. Only one type of block is used per row.

The LatticeECP3 devices contain one or more rows of sysMEM EBR blocks. sysMEM EBRs are large, dedicated

18Kbit fast memory blocks. Each sysMEM block can be configured in a variety of depths and widths as RAM or

ROM. In addition, LatticeECP3 devices contain up to two rows of DSP slices. Each DSP slice has multipliers and

adder/accumulators, which are the building blocks for complex signal processing capabilities.

The LatticeECP3 devices feature up to 16 embedded 3.2Gbps SERDES (Serializer / Deserializer) channels. Each

SERDES channel contains independent 8b/10b encoding / decoding, polarity adjust and elastic buffer logic. Each

group of four SERDES channels, along with its Physical Coding Sub-layer (PCS) block, creates a quad. The func-

tionality of the SERDES/PCS quads can be controlled by memory cells set during device configuration or by regis-

ters that are addressable during device operation. The registers in every quad can be programmed via the

SERDES Client Interface (SCI). These quads (up to four) are located at the bottom of the devices.

Each PIC block encompasses two PIOs (PIO pairs) with their respective sysI/O buffers. The sysI/O buffers of the

LatticeECP3 devices are arranged in seven banks, allowing the implementation of a wide variety of I/O standards.

In addition, a separate I/O bank is provided for the programming interfaces. 50% of the PIO pairs on the left and

right edges of the device can be configured as LVDS transmit/receive pairs. The PIC logic also includes pre-engi-

neered support to aid in the implementation of high speed source synchronous standards such as XGMII, 7:1

LVDS, along with memory interfaces including DDR3.

Other blocks provided include PLLs, DLLs and configuration functions. The LatticeECP3 architecture provides two

Delay Locked Loops (DLLs) and up to ten Phase Locked Loops (PLLs). The PLL and DLL blocks are located at the

end of the EBR/DSP rows.

The configuration block that supports features such as configuration bit-stream decryption, transparent updates

and dual-boot support is located toward the center of this EBR row. Every device in the LatticeECP3 family sup-

ports a sysCONFIG™ port located in the corner between banks one and two, which allows for serial or parallel

device configuration.

In addition, every device in the family has a JTAG port. This family also provides an on-chip oscillator and soft error

detect capability. The LatticeECP3 devices use 1.2V as their core voltage.

LatticeECP3 Family Data Sheet

Architecture

剩余140页未读，继续阅读

评论收藏

内容反馈

北境守望者

粉丝: 0
资源: 1

LATTICE-ECP3-datasheet

LatticeECP3 Family Data Sheet

LatticeECP3EAFamilyDataSheet

lattice ECP3 serdes guide

Lattice ECP3 简介和设计注意事项

Lattice ECP5 和 ECP5-5G系列FPGA 官方技术文档资料合集.zip

Lattice FPGA LFE3-35EA+SRAM VGA视频评估板ALTIUM设计硬件原理图+PCB文件.zip

DDR3 Demo for the Lattice ECP3 Versa Evaluation Board Users Guide

最新LATTICE ECP5 ECP3系列FPGA原理图库（ALITUM库）.SchLib

lattice-ecp3-config.rar_Lattice fpga_config fpga_lattice_lattice

lattice-ecp3-config.rar_Lattice fpga_config fpga_lattice JTAG_li

Lattice ECP3 FPGA 的加密方法

FPGA-TN-02032-1-2-ECP5-ECP5G-sysIO-Usage-Guide_lattice_

LATTICE ECP5 Datasheet

Lattice ECP5(LFE5UM5G-85F-8BG381) FPGA评估板硬件资料包括开发板的PDF原理图.zip

lattice-Boltzmann method

Lattice FPGA -- MachXO2 Family DataSheet

Lattice- Mico32内部培训教材

Lattice FPGA CPLD Semiconductor 全系列芯片原理图库+PCB封装库（AD集成库）.zip

Lattice FPGA ECP2.IntLib

基于新词发现和Lattice-LSTM的中文医疗命名实体识别.pdf

lattice-lstm代码，用于学习交流

Lattice-Boltzmann-Methods-for-Shallow-Water-Flows.pdf

Lattice-Gas Cellular Automata and Lattice Boltzmann Models An Introduction.pdf

NIST FIPS 203 Module-Lattice-Based.pdf

Lattices in Crypto Intro to Lattice-based cryptography

主流LATTICE ECP5 ECP3系列FPGA&CPLD原理图库（ALITUM库）.SchLib

Lattice-based_RLS_Algorithms_Latticefilter_adaptivefilter_algori

Lattice-screen-progressive-scan.rar_lattice_点阵屏

Aliu-2020-Lattice-boltzmann-application-to-na_LBM_

VHDL经典经验-FPGA-Altera-Xilinx-Lattice-Verilog

最新资源