普中-STM32F103C8T6例程.zip

; generated by ARM C/C++ Compiler with , RVCT4.0 [Build 524] for uVision ; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\Out\stm32f10x_tim.o --depend=.\Out\stm32f10x_tim.d --device=DARMSTM --apcs=interwork -O0 -I..\inc -I..\..\..\Libraries\CMSIS\Core\CM3 -I..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc -I..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I"D:\Program Files\KeilARM350\ARM\INC\ST\STM32F10x" ..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c] THUMB AREA ||i.TI1_Config||, CODE, READONLY, ALIGN=1 TI1_Config PROC ;;;2696 */ ;;;2697 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, 000000 b5f0 PUSH {r4-r7,lr} ;;;2698 uint16_t TIM_ICFilter) ;;;2699 { ;;;2700 uint16_t tmpccmr1 = 0, tmpccer = 0; 000002 2400 MOVS r4,#0 000004 2500 MOVS r5,#0 ;;;2701 /* Disable the Channel 1: Reset the CC1E Bit */ ;;;2702 TIMx->CCER &= CCER_CC1E_Reset; 000006 8c06 LDRH r6,[r0,#0x20] 000008 f64f77fe MOV r7,#0xfffe 00000c 403e ANDS r6,r6,r7 00000e 8406 STRH r6,[r0,#0x20] ;;;2703 tmpccmr1 = TIMx->CCMR1; 000010 8b04 LDRH r4,[r0,#0x18] ;;;2704 tmpccer = TIMx->CCER; 000012 8c05 LDRH r5,[r0,#0x20] ;;;2705 /* Select the Input and set the filter */ ;;;2706 tmpccmr1 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask; 000014 f64f760c MOV r6,#0xff0c 000018 4034 ANDS r4,r4,r6 ;;;2707 tmpccmr1 |= TIM_ICSelection | (uint16_t)(TIM_ICFilter << 4); 00001a 051e LSLS r6,r3,#20 00001c ea424616 ORR r6,r2,r6,LSR #16 000020 4334 ORRS r4,r4,r6 ;;;2708 /* Select the Polarity and set the CC1E Bit */ ;;;2709 tmpccer &= CCER_CC1P_Reset; 000022 1e7e SUBS r6,r7,#1 000024 4035 ANDS r5,r5,r6 ;;;2710 tmpccer |= TIM_ICPolarity | CCER_CC1E_Set; 000026 f0410601 ORR r6,r1,#1 00002a 4335 ORRS r5,r5,r6 ;;;2711 /* Write to TIMx CCMR1 and CCER registers */ ;;;2712 TIMx->CCMR1 = tmpccmr1; 00002c 8304 STRH r4,[r0,#0x18] ;;;2713 TIMx->CCER = tmpccer; 00002e 8405 STRH r5,[r0,#0x20] ;;;2714 } 000030 bdf0 POP {r4-r7,pc} ;;;2715 ENDP AREA ||i.TI2_Config||, CODE, READONLY, ALIGN=1 TI2_Config PROC ;;;2735 */ ;;;2736 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, 000000 b5f0 PUSH {r4-r7,lr} ;;;2737 uint16_t TIM_ICFilter) ;;;2738 { ;;;2739 uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; 000002 2400 MOVS r4,#0 000004 2500 MOVS r5,#0 000006 2600 MOVS r6,#0 ;;;2740 /* Disable the Channel 2: Reset the CC2E Bit */ ;;;2741 TIMx->CCER &= CCER_CC2E_Reset; 000008 8c07 LDRH r7,[r0,#0x20] 00000a f64f7cef MOV r12,#0xffef 00000e ea07070c AND r7,r7,r12 000012 8407 STRH r7,[r0,#0x20] ;;;2742 tmpccmr1 = TIMx->CCMR1; 000014 8b04 LDRH r4,[r0,#0x18] ;;;2743 tmpccer = TIMx->CCER; 000016 8c05 LDRH r5,[r0,#0x20] ;;;2744 tmp = (uint16_t)(TIM_ICPolarity << 4); 000018 050f LSLS r7,r1,#20 00001a 0c3e LSRS r6,r7,#16 ;;;2745 /* Select the Input and set the filter */ ;;;2746 tmpccmr1 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask; 00001c f64047ff MOV r7,#0xcff 000020 403c ANDS r4,r4,r7 ;;;2747 tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); 000022 071f LSLS r7,r3,#28 000024 ea444417 ORR r4,r4,r7,LSR #16 ;;;2748 tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); 000028 0617 LSLS r7,r2,#24 00002a ea444417 ORR r4,r4,r7,LSR #16 ;;;2749 /* Select the Polarity and set the CC2E Bit */ ;;;2750 tmpccer &= CCER_CC2P_Reset; 00002e f64f77df MOV r7,#0xffdf 000032 403d ANDS r5,r5,r7 ;;;2751 tmpccer |= tmp | CCER_CC2E_Set; 000034 f0460710 ORR r7,r6,#0x10 000038 433d ORRS r5,r5,r7 ;;;2752 /* Write to TIMx CCMR1 and CCER registers */ ;;;2753 TIMx->CCMR1 = tmpccmr1 ; 00003a 8304 STRH r4,[r0,#0x18] ;;;2754 TIMx->CCER = tmpccer; 00003c 8405 STRH r5,[r0,#0x20] ;;;2755 } 00003e bdf0 POP {r4-r7,pc} ;;;2756 ENDP AREA ||i.TI3_Config||, CODE, READONLY, ALIGN=1 TI3_Config PROC ;;;2776 */ ;;;2777 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, 000000 b5f0 PUSH {r4-r7,lr} ;;;2778 uint16_t TIM_ICFilter) ;;;2779 { ;;;2780 uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; 000002 2400 MOVS r4,#0 000004 2500 MOVS r5,#0 000006 2600 MOVS r6,#0 ;;;2781 /* Disable the Channel 3: Reset the CC3E Bit */ ;;;2782 TIMx->CCER &= CCER_CC3E_Reset; 000008 8c07 LDRH r7,[r0,#0x20] 00000a f64f6cff MOV r12,#0xfeff 00000e ea07070c AND r7,r7,r12 000012 8407 STRH r7,[r0,#0x20] ;;;2783 tmpccmr2 = TIMx->CCMR2; 000014 8b84 LDRH r4,[r0,#0x1c] ;;;2784 tmpccer = TIMx->CCER; 000016 8c05 LDRH r5,[r0,#0x20] ;;;2785 tmp = (uint16_t)(TIM_ICPolarity << 8); 000018 060f LSLS r7,r1,#24 00001a 0c3e LSRS r6,r7,#16 ;;;2786 /* Select the Input and set the filter */ ;;;2787 tmpccmr2 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask; 00001c f64f770c MOV r7,#0xff0c 000020 403c ANDS r4,r4,r7 ;;;2788 tmpccmr2 |= TIM_ICSelection | (uint16_t)(TIM_ICFilter << 4); 000022 051f LSLS r7,r3,#20 000024 ea424717 ORR r7,r2,r7,LSR #16 000028 433c ORRS r4,r4,r7 ;;;2789 /* Select the Polarity and set the CC3E Bit */ ;;;2790 tmpccer &= CCER_CC3P_Reset; 00002a f64f57ff MOV r7,#0xfdff 00002e 403d ANDS r5,r5,r7 ;;;2791 tmpccer |= tmp | CCER_CC3E_Set; 000030 f4467780 ORR r7,r6,#0x100 000034 433d ORRS r5,r5,r7 ;;;2792 /* Write to TIMx CCMR2 and CCER registers */ ;;;2793 TIMx->CCMR2 = tmpccmr2; 000036 8384 STRH r4,[r0,#0x1c] ;;;2794 TIMx->CCER = tmpccer; 000038 8405 STRH r5,[r0,#0x20] ;;;2795 } 00003a bdf0 POP {r4-r7,pc} ;;;2796 ENDP AREA ||i.TI4_Config||, CODE, READONLY, ALIGN=1 TI4_Config PROC ;;;2816 */ ;;;2817 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, 000000 b5f0 PUSH {r4-r7,lr} ;;;2818 uint16_t TIM_ICFilter) ;;;2819 { ;;;2820 uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; 000002 2400 MOVS r4,#0 000004 2500 MOVS r5,#0 000006 2600 MOVS r6,#0 ;;;2821 /* Disable the Channel 4: Reset the CC4E Bit */ ;;;2822 TIMx->CCER &= CCER_CC4E_Reset; 000008 8c07 LDRH r7,[r0,#0x20] 00000a f64e7cff MOV r12,#0xefff 00000e ea07070c AND r7,r7,r12 000012 8407 STRH r7,[r0,#0x20]