/******************************************************************************
*
* Copyright (C) 2018 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file psu_init.c
*
* This file is automatically generated
*
*****************************************************************************/
#include <xil_io.h>
#include <sleep.h>
#include "psu_init.h"
#define DPLL_CFG_LOCK_DLY 63
#define DPLL_CFG_LOCK_CNT 625
#define DPLL_CFG_LFHF 3
#define DPLL_CFG_CP 3
#define DPLL_CFG_RES 2
static int mask_pollOnValue(u32 add, u32 mask, u32 value);
static int mask_poll(u32 add, u32 mask);
static void mask_delay(u32 delay);
static u32 mask_read(u32 add, u32 mask);
static
void PSU_Mask_Write(unsigned long offset, unsigned long mask,
unsigned long val)
{
unsigned long RegVal = 0x0;
RegVal = Xil_In32(offset);
RegVal &= ~(mask);
RegVal |= (val & mask);
Xil_Out32(offset, RegVal);
}
void prog_reg(unsigned long addr, unsigned long mask,
unsigned long shift, unsigned long value) {
int rdata = 0;
rdata = Xil_In32(addr);
rdata = rdata & (~mask);
rdata = rdata | (value << shift);
Xil_Out32(addr, rdata);
}
unsigned long psu_pll_init_data(void)
{
/*
* RPLL INIT
*/
/*
* Register : RPLL_CFG @ 0XFF5E0034
* PLL loop filter resistor control
* PSU_CRL_APB_RPLL_CFG_RES 0xc
* PLL charge pump control
* PSU_CRL_APB_RPLL_CFG_CP 0x3
* PLL loop filter high frequency capacitor control
* PSU_CRL_APB_RPLL_CFG_LFHF 0x3
* Lock circuit counter setting
* PSU_CRL_APB_RPLL_CFG_LOCK_CNT 0x307
* Lock circuit configuration settings for lock windowsize
* PSU_CRL_APB_RPLL_CFG_LOCK_DLY 0x3f
* Helper data. Values are to be looked up in a table from Data Sheet
* (OFFSET, MASK, VALUE) (0XFF5E0034, 0xFE7FEDEFU ,0x7E60EC6CU)
*/
PSU_Mask_Write(CRL_APB_RPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E60EC6CU);
/*##################################################################### */
/*
* UPDATE FB_DIV
*/
/*
* Register : RPLL_CTRL @ 0XFF5E0030
* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
* s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
* ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
* PSU_CRL_APB_RPLL_CTRL_PRE_SRC 0x0
* The integer portion of the feedback divider to the PLL
* PSU_CRL_APB_RPLL_CTRL_FBDIV 0x30
* This turns on the divide by 2 that is inside of the PLL. This does not c
* hange the VCO frequency, just the output frequency
* PSU_CRL_APB_RPLL_CTRL_DIV2 0x1
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00717F00U ,0x00013000U)
*/
PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00717F00U, 0x00013000U);
/*##################################################################### */
/*
* BY PASS PLL
*/
/*
* Register : RPLL_CTRL @ 0XFF5E0030
* Bypasses the PLL clock. The usable clock will be determined from the POS
* T_SRC field. (This signal may only be toggled after 4 cycles of the old
* clock and 4 cycles of the new clock. This is not usually an issue, but d
* esigners must be aware.)
* PSU_CRL_APB_RPLL_CTRL_BYPASS 1
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000008U)
*/
PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U);
/*##################################################################### */
/*
* ASSERT RESET
*/
/*
* Register : RPLL_CTRL @ 0XFF5E0030
* Asserts Reset to the PLL. When asserting reset, the PLL must already be
* in BYPASS.
* PSU_CRL_APB_RPLL_CTRL_RESET 1
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000001U)
*/
PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U);
/*##################################################################### */
/*
* DEASSERT RESET
*/
/*
* Register : RPLL_CTRL @ 0XFF5E0030
* Asserts Reset to the PLL. When asserting reset, the PLL must already be
* in BYPASS.
* PSU_CRL_APB_RPLL_CTRL_RESET 0
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000000U)
*/
PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U);
/*##################################################################### */
/*
* CHECK PLL STATUS
*/
/*
* Register : PLL_STATUS @ 0XFF5E0040
* RPLL is locked
* PSU_CRL_APB_PLL_STATUS_RPLL_LOCK 1
* (OFFSET, MASK, VALUE) (0XFF5E0040, 0x00000002U ,0x00000002U)
*/
mask_poll(CRL_APB_PLL_STATUS_OFFSET, 0x00000002U);
/*##################################################################### */
/*
* REMOVE PLL BY PASS
*/
/*
* Register : RPLL_CTRL @ 0XFF5E0030
* Bypasses the PLL clock. The usable clock will be determined from the POS
* T_SRC field. (This signal may only be toggled after 4 cycles of the old
* clock and 4 cycles of the new clock. This is not usually an issue, but d
* esigners must be aware.)
* PSU_CRL_APB_RPLL_CTRL_BYPASS 0
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000000U)
*/
PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U);
/*##################################################################### */
/*
* Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048
* Divisor value for this clock.
* PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0 0x2
* Control for a clock that will be generated in the LPD, but used in the F
* PD as a clock source for the peripheral clock muxes.
* (OFFSET, MASK, VALUE) (0XFF5E0048, 0x00003F00U ,0x00000200U)
*/
PSU_Mask_Write(CRL_APB_RPLL_TO_FPD_CTRL_OFFSET,
0x00003F00U, 0x00000200U);
/*###
xazu3eg_4G_release.rar （121个子文件） 
design_1.bd 98KB design_1.bxml 5KB psu_init.c 902KB psu_init_gpl.c 901KB design_1_zynq_ultra_ps_e_0_0.cpp 11KB xilinx_zynqmp.cpp 8KB design_1_auto_ds_0.dcp 507KB design_1_zynq_ultra_ps_e_0_0.dcp 402KB design_1_auto_pc_0.dcp 250KB design_1_axi_gpio_0_0.dcp 37KB design_1_rst_ps8_0_99M_0.dcp 21KB libps8.dll 479KB libremoteport.dll 360KB psu_init.h 1.59MB psu_init_gpl.h 1.59MB zynq_ultra_ps_e_tlm.h 13KB xilinx_zynqmp.h 5KB design_1_zynq_ultra_ps_e_0_0.h 5KB
psu_init.html 55KB design_1_zynq_ultra_ps_e_0_0.hwdef 808KB design_1.hwdef 37KB design_1.hwh 193KB design_1.protoinst 15KB libps8.so 386KB libremoteport.so 62KB zynq_ultra_ps_e_vip_v1_0_4_reg_params.sv 1.77MB zynq_ultra_ps_e_vip_v1_0_4_reg_init.sv 1.03MB zynq_ultra_ps_e_vip_v1_0_vl_rfs.sv 412KB design_1_zynq_ultra_ps_e_0_0.sv 62KB zynq_ultra_ps_e_vip_v1_0_4_apis.sv 47KB zynq_ultra_ps_e_vip_v1_0_4_axi_gp.sv 38KB axi_vip_v1_1_vl_rfs.sv 30KB zynq_ultra_ps_e_vip_v1_0_4_unused_ports.sv 24KB zynq_ultra_ps_e_vip_v1_0_4_local_params.sv 7KB zynq_ultra_ps_e_vip_v1_0_4_axi_ace.sv 4KB zynq_ultra_ps_e_vip_v1_0_4_axi_acp.sv 4KB design_1_zynq_ultra_ps_e_0_0_stub.sv 4KB psu_init.tcl 860KB design_1_bd.tcl 79KB bd_1f5defd0.ui 912B design_1_auto_ds_0_sim_netlist.v 780KB axi_dwidth_converter_v2_1_vlsyn_rfs.v 603KB axi_dwidth_converter_v2_1_vl_rfs.v 603KB fifo_generator_v13_2_rfs.v 582KB fifo_generator_vlog_beh.v 442KB design_1_zynq_ultra_ps_e_0_0_sim_netlist.v 424KB design_1_auto_pc_0_sim_netlist.v 383KB zynq_ultra_ps_e_v3_2_2.v 224KB axi_protocol_converter_v2_1_vl_rfs.v 218KB blk_mem_gen_v8_4.v 167KB axi_register_slice_v2_1_vl_rfs.v 121KB generic_baseblocks_v2_1_vl_rfs.v 109KB axi_clock_converter_v2_1_vl_rfs.v 100KB axi_data_fifo_v2_1_vl_rfs.v 71KB design_1_zynq_ultra_ps_e_0_0.v 53KB design_1_axi_gpio_0_0_sim_netlist.v 50KB design_1.v 40KB design_1.v 40KB axi_infrastructure_v1_1_vl_rfs.v 29KB design_1_rst_ps8_0_99M_0_sim_netlist.v 24KB design_1_zynq_ultra_ps_e_0_0_vip_wrapper.v 18KB design_1_auto_ds_0.v 16KB design_1_auto_ds_0.v 16KB design_1_auto_pc_0.v 14KB design_1_auto_pc_0.v 13KB design_1_auto_ds_0_stub.v 5KB design_1_auto_pc_0_stub.v 4KB design_1_zynq_ultra_ps_e_0_0_stub.v 4KB design_1_axi_gpio_0_0_stub.v 2KB design_1_rst_ps8_0_99M_0_stub.v 2KB design_1_wrapper.v 1KB hw_rst.v 528B axi_infrastructure_v1_1_0.vh 8KB blk_mem_gen_v8_4_vhsyn_rfs.vhd 14.18MB fifo_generator_v13_2_vhsyn_rfs.vhd 2.34MB fifo_generator_v13_2_rfs.vhd 1.38MB axi_lite_ipif_v3_0_vh_rfs.vhd 124KB axi_gpio_v2_0_vh_rfs.vhd 79KB proc_sys_reset_v5_0_vh_rfs.vhd 70KB interrupt_control_v3_1_vh_rfs.vhd 56KB lib_cdc_v1_0_rfs.vhd 49KB design_1_axi_gpio_0_0.vhd 11KB design_1_axi_gpio_0_0.vhd 10KB design_1_rst_ps8_0_99M_0.vhd 8KB design_1_rst_ps8_0_99M_0.vhd 7KB design_1_auto_ds_0_sim_netlist.vhdl 1.02MB design_1_auto_pc_0_sim_netlist.vhdl 466KB design_1_zynq_ultra_ps_e_0_0_sim_netlist.vhdl 431KB design_1_axi_gpio_0_0_sim_netlist.vhdl 61KB design_1_rst_ps8_0_99M_0_sim_netlist.vhdl 34KB design_1_auto_ds_0_stub.vhdl 6KB design_1_auto_pc_0_stub.vhdl 5KB design_1_zynq_ultra_ps_e_0_0_stub.vhdl 4KB design_1_axi_gpio_0_0_stub.vhdl 2KB design_1_rst_ps8_0_99M_0_stub.vhdl 2KB design_1_zynq_ultra_ps_e_0_0.xci 524KB design_1_ps8_0_axi_periph_0.xci 42KB design_1_auto_ds_0.xci 27KB design_1_auto_pc_0.xci 27KB design_1_axi_gpio_0_0.xci 17KB共 121 条
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