X1226芯片资料X1226芯片资料_x1226是什么芯片资源-CSDN文库

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X1226芯片资料 X1226芯片是一款实时时钟（RTC）芯片，具有时钟 تقوim功能、两个可编程的报警器和512x8位的EEPROM存储器，以及振荡器补偿和电池备份开关。该芯片的振荡器使用外部低成本的32.768kHz晶体振荡器，所有补偿和trim组件都集成在芯片上，消除了多个外部离散组件和trim电容，从而节省了pcb面积和组件成本。 1. 时钟/日历功能： X1226芯片具有实时时钟和日历功能，可以追踪小时、分钟、秒、星期、日、月和年。该芯片还具有两个可编程的报警器，可以设置在某个特定的时间点或日期，例如，设置报警器在每天早上的7点钟响铃。 2.振荡器补偿： X1226芯片的振荡器具有补偿功能，可以补偿振荡器的频率漂移，确保时钟的准确性。该芯片的振荡器补偿电路包括内部反馈电阻和补偿电容，以及64个数字控制trim电容，可以在±30ppm的范围内调整振荡器的频率。 3. EEPROM存储器： X1226芯片具有512x8位的EEPROM存储器，可以存储大量的数据。该存储器具有64字节的页面写入模式、8种保护模式和单字节写入能力，确保数据的安全和可靠性。 4. 低功率CMOS设计： X1226芯片采用低功率CMOS设计，典型的工作电流仅为1.25µA，非常适合电池供电的应用场景。 5. Two-Wire™接口： X1226芯片具有Two-Wire™接口，兼容I2C标准，支持400kHz的数据传输速率，非常适合需要高速数据传输的应用场景。 6. 频率输出： X1226芯片具有频率输出功能，可以输出1Hz、4096Hz或32.768kHz的频率信号，非常适合需要频率同步的应用场景。 7. 应用场景： X1226芯片广泛应用于各种电子设备中，例如utility meters、HVAC设备、音频/视频组件、Set Top Box/电视机、Modems、网络路由器、_cellsular Infrastructure Equipment、Fixed Broadband Wireless Equipment、Pagers/PDA、POS设备、测试仪器/fixture、办公自动化设备、家用电器和计算机产品等。 X1226芯片是一款功能强大且灵活的RTC芯片，非常适合需要时钟/日历功能、EEPROM存储器和低功率设计的应用场景。

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REV 1.1.24 1/13/03

Characteristics subject to change without notice.

1 of 24

www.xicor.com

4K (512 x 8)

2-Wire

™

RTC

Real Time Clock/Calendar with EEPROM

FEATURES

• Real Time Clock/Calendar

—Tracks time in Hours, Minutes, and Seconds

—Day of the Week, Day, Month, and Year

• 2 Polled Alarms (Non-volatile)

—Settable on the Second, Minute, Hour, Day of

the Week, Day, or Month

—Repeat Mode (periodic interrupts)

• Oscillator Compensation on chip

—Internal feedback resistor and compensation

capacitors

—64 position Digitally Controlled Trim Capacitor

—6 digital frequency adjustment settings to

±30ppm

• Battery Switch or Super Cap Input

• 512 x 8 Bits of EEPROM

—64-Byte Page Write Mode

—8 modes of Block Lock™

Protection

—Single Byte Write Capability

• High Reliability

—Data Retention: 100 years

—Endurance: 100,000 cycles per byte

• 2-Wire™ Interface interoperable with I2C*

—400kHz data transfer rate

• Frequency Output (SW Selectable: Off, 1Hz,

4096Hz or 32.768kHz)

• Low Power CMOS

—1.25µA Operating Current (Typical)

• Small Package Options

—8-Lead SOIC and 8-Lead TSSOP

APPLICATIONS

• Utility Meters

• HVAC Equipment

• Audio / Video Components

• Set Top Box / Television

• Modems

• Network Routers, Hubs, Switches, Bridges

• Cellular Infrastructure Equipment

• Fixed Broadband Wireless Equipment

• Pagers / PDA

• POS Equipment

• Test Meters / Fixtures

• Ofﬁce Automation (Copiers, Fax)

• Home Appliances

• Computer Products

• Other Industrial / Medical / Automotive

DESCRIPTION

The X1226 device is a Real Time Clock with clock/

calendar, two polled alarms with integrated 512x8

EEPROM, oscillator compensation, and battery

backup switch.

The oscillator uses an external, low-cost 32.768kHz

crystal. All compensation and trim components are

integrated on the chip. This eliminates several external

discrete components and a trim capacitor, saving

board area and component cost.

X1226

BLOCK DIAGRAM

Oscillator

Frequency

Timer

Logic

Divider

Calendar

Control/

Registers

1Hz

Time

Keeping

Registers

Alarm Regs

Compare

Mask

Control

Decode

Logic

Alarm

(EEPROM)

SCL

SDA

Serial

Interface

Decoder

EEPROM

ARRAY

Registers

Status

(SRAM)

Select

PHZ/IRQ

BACK

32.768kHz

(SRAM)

Battery

Circuitry

Switch

OSC

Compensation

*I2C is a Trademark of Philips.

New Features

Repetitive Alarms &

Temperature Compensation

查询X1226供应商

X1226

REV 1.1.24 1/13/03

Characteristics subject to change without notice.

2 of 24

www.xicor.com

DESCRIPTION

(continued)

The Real-Time Clock keeps track of time with separate

registers for Hours, Minutes, Seconds. The Calendar

has separate registers for Date, Month, Year and Day-

of-week. The calendar is correct through 2099, with

automatic leap year correction.

The powerful Dual Alarms can be set to any Clock/

Calendar value for a match. For instance, every

minute, every Tuesday, or 5:23 AM on March 21. The

alarms can be polled in the Status Register or provide

a hardware interrupt (IRQ Pin). There is a repeat

mode for the alarms allowing a periodic interrupt.

The PHZ/IRQ pin may be software selected to provide

a frequency output of 1 Hz, 4096 Hz, or 32,768 Hz.

The device offers a backup power input pin. This

BACK

pin allows the device to be backed up by battery

or SuperCap. The entire X1226 device is fully

operational from 2.7 to 5.5 volts and the clock/calendar

portion of the X1226 device remains fully operational

down to 1.8 volts (Standby Mode).

The X1226 device provides 4K bits of EEPROM with 8

modes of BlockLock™ control. The BlockLock allows a

safe, secure memory for critical user and conﬁguration

data, while allowing a large user storage area.

PIN DESCRIPTIONS

Serial Clock (SCL)

The SCL input is used to clock all data into and out of

the device. The input buffer on this pin is always active

(not gated).

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and

out of the device. It has an open drain output and may

be wire ORed with other open drain or open collector

outputs. The input buffer is always active (not gated).

An open drain output requires the use of a pull-up

resistor. The output circuitry controls the fall time of the

output signal with the use of a slope controlled pull-

down. The circuit is designed for 400kHz 2-wire inter-

face speed.

BACK

This input provides a backup supply voltage to the

device. V

BACK

supplies power to the device in the

event the V

supply fails. This pin can be connected

to a battery, a Supercap or tied to ground if not used.

Programmable Frequency/Interrupt Output – PHZ/IRQ

This is either an output from the internal oscillator or an

interrupt signal output. It is an open drain output.

When used as frequency output, this signal has a

frequency of 32.768kHz, 4096Hz, 1Hz or inactive.

When used as interrupt output, this signal notiﬁes a

host processor that an alarm has occurred and an

action is required. It is an active LOW output.

The control bits for this function are FO1 and FO0 and

are found in address 0011h of the Clock Control Mem-

ory map. Refer to “Programmable Frequency Output

Bits” on page 6.

X1, X2

The X1 and X2 pins are the input and output,

respectively, of an inverting ampliﬁer. An external

32.768kHz quartz crystal is used with the X1226 to

supply a timebase for the real time clock. The

recommended crystal is a Citizen CFS206-32.768KDZF.

Internal compensation circuitry is included to form a

complete oscillator circuit. Care should be taken in the

placement of the crystal and the layout of the circuit.

Plenty of ground plane around the device and short

traces to X1 and X2 are highly recommended. See

Application section for more recommendations.

Figure 1. Recommended Crystal connection

POWER CONTROL OPERATION

The power control circuit accepts a V

and a V

BACK

input. The power control circuit powers the clock from

BACK

when V

< V

BACK

– 0.2V. It will switch back to

power the device from V

when V

exceeds V

BACK

NC = No internal connection

BACK

PHZ/IRQ

SCL

SDA

8-Pin TSSOP

X1226

BACK

PHZ/IRQ

SCL

SDA

8-Pin SOIC

X1226

REV 1.1.24 1/13/03

Characteristics subject to change without notice.

3 of 24

www.xicor.com

Figure 2. Power Control

REAL TIME CLOCK OPERATION

The Real Time Clock (RTC) uses an external

32.768kHz quartz crystal to maintain an accurate

internal representation of the second, minute, hour,

day, date, month, and year. The RTC has leap-year

correction. The clock also corrects for months having

fewer than 31 days and has a bit that controls 24 hour

or AM/PM format. When the X1226 powers up after

the loss of both V

and V

BACK

, the clock will not

operate until at least one byte is written to the clock

Reading the Real Time Clock

The RTC is read by initiating a Read command and

specifying the address corresponding to the register of

the Real Time Clock. The RTC Registers can then be

read in a Sequential Read Mode. Since the clock runs

continuously and a read takes a ﬁnite amount of time,

there is the possibility that the clock could change during

the course of a read operation. In this device, the time is

latched by the read command (falling edge of the clock

on the ACK bit prior to RTC data output) into a separate

latch to avoid time changes during the read operation.

The clock continues to run. Alarms occurring during a

read are unaffected by the read operation.

Writing to the Real Time Clock

The time and date may be set by writing to the RTC

registers. To avoid changing the current time by an

uncompleted write operation, the current time value is

loaded into a separate buffer at the falling edge of the

clock on the ACK bit before the RTC data input bytes,

the clock continues to run. The new serial input data

replaces the values in the buffer. This new RTC value

is loaded back into the RTC Register by a stop bit at

the end of a valid write sequence. An invalid write

operation aborts the time update procedure and the

contents of the buffer are discarded. After a valid write

operation the RTC will reﬂect the newly loaded data

beginning with the next “one second” clock cycle after

the stop bit is written. The RTC continues to update

the time while an RTC register write is in progress and

the RTC continues to run during any nonvolatile write

sequences. A single byte may be written to the RTC

without affecting the other bytes.

Accuracy of the Real Time Clock

The accuracy of the Real Time Clock depends on the

frequency of the quartz crystal that is used as the time

base for the RTC. Since the resonant frequency of a

crystal is temperature dependent, the RTC perfor-

mance will also be dependent upon temperature. The

frequency deviation of the crystal is a fuction of the

turnover temperature of the crystal from the crystal’s

nominal frequency. For example, a >20ppm frequency

deviation translates into an accuracy of >1 minute per

month. These parameters are available from the

crystal manufacturer. Xicor’s RTC family provides on-

chip crystal compensation networks to adjust load-

capacitance to tune oscillator frequency from +116

ppm to –37 ppm when using a 12.5 pF load crystal.

For more detail information see the Application

section.

CLOCK/CONTROL REGISTERS (CCR)

The Control/Clock Registers are located in an area

separate from the EEPROM array and are only

accessible following a slave byte of “1101111x” and

reads or writes to addresses [0000h:003Fh]. The

clock/control memory map has memory addresses

from 0000h to 003Fh. The deﬁned addresses are

described in the Table 1. Writing to and reading from

the undeﬁned addresses are not recommended.

CCR Access

The contents of the CCR can be modiﬁed by perform-

ing a byte or a page write operation directly to any

address in the CCR. Prior to writing to the CCR

(except the status register), however, the WEL and

RWEL bits must be set using a two step process (See

section “Writing to the Clock/Control Registers.”)

The CCR is divided into 5 sections. These are:

1. Alarm 0 (8 bytes; non-volatile)

2. Alarm 1 (8 bytes; non-volatile)

3. Control (4 bytes; non-volatile)

4. Real Time Clock (8 bytes; volatile)

5. Status (1 byte; volatile)

BACK

Voltage

Off

X1226

REV 1.1.24 1/13/03

Characteristics subject to change without notice.

4 of 24

www.xicor.com

Table 1. Clock/Control Memory Map

Addr. Type

Reg

Name

Bit

Range

Default

76543210

(optional)

003F Status SR BAT AL1 AL0 0 0 RWEL WEL RTCF 01h

0037 RTC

(SRAM)

Y2K 0 0 Y2K21 Y2K20 Y2K13 0 0 Y2K10 19/20 20h

0036 DW 0 0 0 0 0 DY2 DY1 DY0 0-6 00h

0035 YR Y23 Y22 Y21 Y20 Y13 Y12 Y11 Y10 0-99 00h

0034 MO 0 0 0 G20 G13 G12 G11 G10 1-12 00h

0033 DT 0 0 D21 D20 D13 D12 D11 D10 1-31 00h

0032 HR MIL 0 H21 H20 H13 H12 H11 H10 0-23 00h

0031 MN 0 M22 M21 M20 M13 M12 M11 M10 0-59 00h

0030 SC 0 S22 S21 S20 S13 S12 S11 S10 0-59 00h

0013 Control

(EEPROM)

DTR 0 0 0 0 0 DTR2 DTR1 DTR0 00h

0012 ATR 0 0 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 00h

0011 INT IM AL1E AL0E FO1 FO0 X X X 00h

0010 BL BP2 BP1 BP0 00000 00h

000F Alarm1

(EEPROM)

Y2K1 0 0 A1Y2K21 A1Y2K20 A1Y2K13 0 0 A1Y2K10 19/20 20h

000E DWA1 EDW1 0 0 0 0 DY2 DY1 DY0 0-6 00h

000D YRA1 Unused - Default = RTC Year value (No EEPROM) - Future expansion

000C MOA1 EMO1 0 0 A1G20 A1G13 A1G12 A1G11 A1G10 1-12 00h

000B DTA1 EDT1 0 A1D21 A1D20 A1D13 A1D12 A1D11 A1D10 1-31 00h

000A HRA1 EHR1 0 A1H21 A1H20 A1H13 A1H12 A1H11 A1H10 0-23 00h

0009 MNA1 EMN1 A1M22 A1M21 A1M20 A1M13 A1M12 A1M11 A1M10 0-59 00h

0008 SCA1 ESC1 A1S22 A1S21 A1S20 A1S13 A1S12 A1S11 A1S10 0-59 00h

0007 Alarm0

(EEPROM)

Y2K0 0 0 A0Y2K21 A0Y2K20 A0Y2K13 0 0 A0Y2K10 19/20 20h

0006 DWA0 EDW0 0 0 0 0 DY2 DY1 DY0 0-6 00h

0005 YRA0 Unused - Default = RTC Year value (No EEPROM) - Future expansion

0004 MOA0 EMO0 0 0 A0G20 A0G13 A0G12 A0G11 A0G10 1-12 00h

0003 DTA0 EDT0 0 A0D21 A0D20 A0D13 A0D12 A0D11 A0D10 1-31 00h

0002 HRA0 EHR0 0 A0H21 A0H20 A0H13 A0H12 A0H11 A0H10 0-23 00h

0001 MNA0 EMN0 A0M22 A0M21 A0M20 A0M13 A0M12 A0M11 A0M10 0-59 00h

0000 SCA0 ESC0 A0S22 A0S21 A0S20 A0S13 A0S12 A0S11 A0S10 0-59 00h

Each register is read and written through buffers. The

non-volatile portion (or the counter portion of the RTC) is

updated only if RWEL is set and only after a valid write

operation and stop bit. A sequential read or page write

operation provides access to the contents of only one

section of the CCR per operation. Access to another sec-

tion requires a new operation. Continued reads or writes,

once reaching the end of a section, will wrap around to

the start of the section. A read or write can begin at any

address in the CCR.

It is not necessary to set the RWEL bit prior to writing

the status register. Section 5 (status register) supports

a single byte read or write only. Continued reads or

writes from this section terminates the operation.

The state of the CCR can be read by performing a ran-

dom read at any address in the CCR at any time. This

returns the contents of that register location. Addi-

tional registers are read by performing a sequential

read. The read instruction latches all Clock registers

into a buffer, so an update of the clock does not

change the time being read. A sequential read of the

CCR will not result in the output of data from the mem-

ory array. At the end of a read, the master supplies a

stop condition to end the operation and free the bus.

After a read of the CCR, the address remains at the

previous address +1 so the user can execute a current

address read of the CCR and continue reading the

next Register.

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