CORE-V Cores Roadmap
1
© OpenHW Group
October 2021
Davide Schiavone davideⓐopenhwgroup.org
Jérôme Quévremont jerome
·
quevremontⓐthalesgroup
·
com
Arjan Bink arjan.binkⓐsilabs.com
CORE-V Family History
• Initial contribution of open-source RISC-V cores from ETH Zurich PULP Platform and the
OpenHW Group is the official committer for these repositories
• OpenHW Cores Task Group has the mandate to develop feature and functionality
roadmap for the CORE-V Family of open-source RISC-V processors
• Chair: Arjan Bink, Silicon Laboratories
• Vice-Chair: Jérôme Quévremont, Thales Research & Technology
October 2021
2
© OpenHW Group
Core
Bits/Stage
s Description
CV32E40P
(RI5CY)
32bit /
4-stage
A family of 4-stage cores that implement, RV32IMFCXpulp, optional 32-bit FPU, instruction
set extensions for DSP operations including HW loops, SIMD extensions, bit manipulation
and post-increment instructions.
CVA6
(Ariane)
32 & 64bit /
6-stage
A family of 6-stage, single issue, in-order CPU cores implementing RV64GC extensions
with three privilege levels M, S, U to fully support a Unix-like (Linux, BSD, etc.) operating
system. The cores have configurable size, separate TLBs, a hardware PTW and
branch-prediction (branch target buffer, branch history table and a return address stack).
CORE-V P/Ns, Gates, TRLs
Reference Material
October 2021
© OpenHW Group
3
CORE-V Cores P/N Syntax
October 2021
© OpenHW Group
4
CV32E40P
FAMILY
CORE-V
WL
word-length
CLASS
Embedded,
Application
IDENTITY
pipe length,
version
MODIFIER
special
cases
OpenHW Project Framework
October 2021
© OpenHW Group
5
PC
Project Concept
PL
Project Launch
PA
Plan Approved
PF
Project Freeze
Green-light of
project concept by
TWG
Proposed scope, initial
view of the components
and features, why do this
project?
Purpose
CriteriaGate
Full project launch
approval by TWG
Outline of the requirements,
features, components,
project supporters, risks,
high level schedule
Communicate project
plan to TWG, (allowing
member participation
and review
Project plan full checklist,
project methodology. initial
agile backlog, requirements
specification
Completion of
releasable project
content
RTL Freeze checklist or other
final checklist has been
completed
Project work
