# Cortex-M0 implementation on a Kintex-7 FPGA
## Overview
Soft-microcontroller implementation of an ARM Cortex-M0 into a KC705. This project implements a design that contains the following components:
- **Cortex-M0 obfuscated core**: core provided by the ARM DesignStart website
- **RAM memory**: implementation of a RAM memory that accepts an initialization file
- **AHB3-lite interconnection**: interconnection responsible for allowing the communication between masters and slaves in AHB3-lite protocol
- **Pattern detector**: Core that implements a simple state machine that toggles its output when the pattern "f0f0f0f0" is seen on its input bus
When the board is turned on, the cortex-m0 reads the RAM memory, which was synthesized with a program that counts up to a fixed number and then puts the pattern "f0f0f0f0" at the bus. This causes the pattern detector to toggle its output, which it connected to an LED. For the synthesis, the program is defined to count up to 10,000,000. For simulation purposes, a memory file with a program that counts up to 200 is available.
## Requirements
The tools used in this project are listed below. However, it can be ported to different vendor/boards thanks to the flexibility provided by [hdlmake](https://www.ohwr.org/projects/hdl-make).
- Vivado
- KC705 Evaluation board
- Hdlmake
- ARM Cortex-M0 DesignStart processor, available at [ARM Design Start website](https://www.arm.com/resources/designstart)
## Instructions
- Clone the repository with its submodules:
```sh
$ git clone --recurse-submodules git@github.com:vfinotti/cortex-m0-soft-microcontroller.git
```
- Change the directory to the synthesis folder
```sh
$ cd ./syn/kc705_blinky/verilog/
```
- Copy the files "cortexm0ds_logic.v" and "CORTEXM0INTEGRATION.v" (obtained from the ARM DesignStart website) to *modules/cortex-m0/verilog/*
- run hdlmake to generate the Makefile, and then make the project
```sh
$ hdlmake
$ make
```
<!-- Include instructions for generating the memory file with arm-gcc -->
## References
1. <http://web.fi.uba.ar/~pmartos/publicaciones/ApplicationNoteCortexM0.pdf>: Project which inspired this work
2. <https://static.docs.arm.com/ddi0432/c/DDI0432C_cortex_m0_r0p0_trm.pdf>: Cortex-M0 Technical Reference Manual
3. <https://silver.arm.com/download/download.tm?pv=1085658>: AMBA 3 AHB-Lite Protocol Specification
ARM Cortex-M0 的软微控制器实现_SystemVerilog_代码_相关文件_下载
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cortex-m0-soft-microcontroller-master.zip （44个子文件） 
cortex-m0-soft-microcontroller-master 
.gitmodules 1KB ip_cores general-cores roa_logic ahb3lite_timer ahb3lite_memory memory ahb3lite_interconnect ahb3lite_pkg ahb3lite_dma vhdl-extras top kc705_busy_wait cm0_busy_wait_top.xdc 2KB verilog Manifest.py 1KB cm0_busy_wait_top.sv 16KB kc705_dma cm0_dma_top.xdc 2KB verilog cm0_dma_top.sv 23KB Manifest.py 1KB kc705_blinky cm0_blinky_top.xdc 2KB verilog Manifest.py 976B cm0_blinky_top.sv 12KB kc705_interruption cm0_interruption_top.xdc 2KB verilog Manifest.py 1KB cm0_interruption_top.sv 17KB LICENSE 1KB sim kc705_busy_wait run_busy_wait_sim.tcl 218B kc705_interrupt run_interrupt_sim.tcl 224B kc705_dma run_dma_sim.tcl 206B kc705_blinky run_blinky_sim.tcl 212B .gitignore 2KB README.md 2KB syn kc705_busy_wait verilog Manifest.py 260B kc705_dma verilog Manifest.py 242B kc705_blinky verilog Manifest.py 251B kc705_interruption verilog Manifest.py 269B modules misc vhdl Manifest.py 62B detection_fsm.vhd 3KB edge_detector.vhd 3KB cortex-m0 vhdl Manifest.py 42B cortex_m0_wrapper.vhd 22KB verilog Manifest.py 68B clk vhdl Manifest.py 32B sys_pll.vhd 8KB memory memory_dma_syn.mem 8KB memory_interrupt_sim.mem 8KB vhdl rl_ram_1r1w_generic.vhd 4KB Manifest.py 44B memory_interrupt_syn.mem 8KB memory_200_sim.mem 3KB memory_dma_sim.mem 8KB memory_dummy.mem 17KB memory_1M_syn.mem 3KB memory_busy_wait.mem 5KB cordic vhdl ahb3lite_cordic.vhd 9KB Manifest.py 39B资源评论
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