# uart register tool
Utility for simply creating and modifying VHDL bus slave modules. uart does not refer to the hardware device!
## Concept
The main goal of the project is to able to automatically create and modify VHLD bus slave modules based on a simple definition format. By employing VHDL records the handling of the registers can be completely hidden in a module seperate from the rest of the designers logic. All referring to the registers are done via a record which specifies if the register is read-only or read-write, and also includes the name. All bus-specific signals are also wrapped in records. This increases the readability of the design as a whole.
## Bus support
uart currently supports these bus-types:
- AXI4-lite
## Requirements
uart is currently only tested with Python 3.5.2
## Getting Started
Install the latest relase by using pip (preferably pip3):
`pip3 install uart`
### Usage
`uart.py FILE [-o DIR]`
`uart.py -c FILE [-o DIR]`
`uart.py -e FILE [-o DIR]`
`uart.py --version`
`uart.py -h | --help`
### Output
The output VHDL files must be compiled with VHDL 2008.
## Latest Development Version (Bleeding Edge)
The latest development version can be found in the [dev branch](https://github.com/olagrottvik/uart/tree/dev) on Github. Clone the repo and checkout the branch.
`git clone https://github.com/olagrottvik/uart.git`
`cd uart`
`git checkout dev`
`pip3 install -r requirements.txt`
`python3 -m uart`
### Examples
The examples folder contain a JSON-file generated by the menu-system. This file is readable to the point that you can create your own from this template alone if you can't bothered with the menu-system. The folder also contain the output files generated based on the JSON-file.
## Release Notes
Release notes can be found at the [Releases page](https://github.com/olagrottvik/uart/releases).
## Contributing
If you have ideas on how to improve the project, please review [CONTRIBUTING.md](CONTRIBUTING.md) for details. Note that we also have a [Code of Conduct](CODE_OF_CONDUCT.md).
## License
This project is licensed under the MIT license - see [LICENSE](LICENSE) for details.
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PyPI 官网下载 | uart-0.6.4.tar.gz
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uart-0.6.4.tar.gz (22个子文件)
uart-0.6.4
PKG-INFO 358B
uart.egg-info
PKG-INFO 358B
requires.txt 82B
SOURCES.txt 378B
entry_points.txt 45B
top_level.txt 5B
dependency_links.txt 1B
uart
bus.py 26KB
editor.py 16KB
vhdl.py 6KB
register.py 7KB
utils.py 9KB
documentation.py 6KB
module.py 28KB
__main__.py 8KB
__init__.py 0B
header.py 4KB
field.py 2KB
exceptions.py 831B
setup.cfg 38B
setup.py 901B
README.md 2KB
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