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VCS VCS user guide VCS用户手册 VCS-userguide-Q-2020.03-SP2
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VCS
®
User Guide
Q-2020.03-SP2, September 2020
Verification Continuum
TM
ii
Copyright Notice and Proprietary Information
© 2020 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys,
Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use,
reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Third-Party Software Notices
VCS® and configurations of VCS includes or is bundled with software licensed to Synopsys under free or open-source
licenses. For additional information regarding Synopsys's use of free and open-source software, refer to the
third_party_notices.txt file included within the <install_path>/doc directory of the installed VCS software.
Destination Control Statement
All technical data contained in this publication is subject to the export control laws of the United States of America.
Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader's responsibility to
determine the applicable regulations and to comply with them.
Disclaimer
SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH
REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
Trademarks
Synopsys and certain Synopsys product names are trademarks of Synopsys, as set forth at
https://www.synopsys.com/company/legal/trademarks-brands.html.
All other product or company names may be trademarks of their respective owners.
Free and Open-Source Software Licensing Notices
If applicable, Free and Open-Source Software (FOSS) licensing notices are available in the product installation.
Third-Party Links
Any links to third-party websites included in this document are for your convenience only. Synopsys does not endorse
and is not responsible for such websites and their practices, including privacy practices, availability, and content.
www.synopsys.com
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Contents
1. Getting Started
Simulator Support with Technologies . . . . . . . . . . . . . . . . . . . . . 1-2
Simulation Preemption Support. . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Setting Up the Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Verifying Your System Configuration . . . . . . . . . . . . . . . . . . . 1-5
Obtaining a License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Setting Up Your Environment. . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Setting Up Your C Compiler. . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Creating a synopsys_sim.setup File . . . . . . . . . . . . . . . . . . . 1-9
The Concept of a Library in VCS . . . . . . . . . . . . . . . . . . . 1-11
Library Name Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Including Other Setup Files . . . . . . . . . . . . . . . . . . . . . . . 1-12
Using the SYNOPSYS_SIM_SETUP Environment Variable 1-13
Supporting VHDL Non-Locally Static Aggregates . . . . . . 1-13
Displaying Setup Information. . . . . . . . . . . . . . . . . . . . . . . . . 1-15
Displaying Design Information Analyzed Into a Library . . . . . 1-16
Using the Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
iv
Feedback
Two-step Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
Compiling the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
Simulating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
Three-step Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
Basic Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Two-step Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Three-step Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Default Time Unit and Time Precision . . . . . . . . . . . . . . . . . . . . . 1-21
Searching Identifiers in the Design Using UNIX Commands . . . 1-22
Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24
2. VCS Flow
Three-step Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Using vhdlan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Using vlogan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Analyzing the Design to Different Libraries . . . . . . . . . . . 2-15
Elaboration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Using VCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Interactive Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Batch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Commonly Used Runtime Options . . . . . . . . . . . . . . . . . . 2-20
Two-step Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
Using vcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
v
Feedback
Interactive Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
Batch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
Commonly Used Runtime Options . . . . . . . . . . . . . . . . . . 2-29
3. Modeling Your Design
Avoiding Race Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Using and Setting a Value at the Same Time . . . . . . . . . . . . 3-3
Setting a Value Twice at the Same Time . . . . . . . . . . . . . . . . 3-3
Flip-Flop Race Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Continuous Assignment Evaluation . . . . . . . . . . . . . . . . . . . . 3-5
Counting Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Time Zero Race Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Race Detection in Verilog Code . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
The Dynamic Race Detection Tool. . . . . . . . . . . . . . . . . . . . . 3-8
Introduction to the Dynamic Race Detection Tool . . . . . . 3-9
Enabling Race Detection . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
The Race Detection Report . . . . . . . . . . . . . . . . . . . . . . . 3-12
Post-Processing the Report . . . . . . . . . . . . . . . . . . . . . . . 3-16
Debugging Simulation Mismatches . . . . . . . . . . . . . . . . . 3-18
The Static Race Detection Tool . . . . . . . . . . . . . . . . . . . . . . . 3-20
Race Detection Tool to Identify Race between Clock and Data . 3-23
Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
Optimizing Testbenches for Debugging. . . . . . . . . . . . . . . . . . . . 3-28
Conditional Compilation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
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