1. About This Application Note
This application note demonstrates how to debug a design with the Signal Tap Logic
Analyzer. The Signal Tap logic analyzer, available in the Intel
®
Quartus
®
Prime Pro
Edition software, captures and displays the real-time signal behavior in an Intel FPGA
design.
You can use the Signal Tap logic analyzer to probe and debug the behavior of internal
signals during normal device operation, without requiring I/O pins or external lab
equipment. For more information on using all of the features of the Signal Tap logic
analyzer, refer to the following available resources.
Related Information
• Intel Quartus Prime Pro Edition User Guide: Debug Tools
• Intel FPGA Technical Training
1.1. Tutorial Prerequisites
Use of this tutorial requires the following:
• Installation and basic familiarity with the Intel Quartus Prime Pro Edition software
version 23.4 or later. The Intel Quartus Prime software includes the Signal Tap
logic analyzer and the Programmer.
• The Intel Arria
®
10 SX SoC Development Kit, or a design board with a JTAG
connection to the device under test (DUT).
• An Intel FPGA Download Cable II (USB-Blaster II), for communication between the
FPGA and the Intel Quartus Prime software.
• The Intel Arria 10 FPGA - Signal Tap Logic Analyzer Getting Started Design
Example, available from the Intel FPGA Design Store.
Related Information
• Intel Quartus Prime Pro Edition User Guide: Getting Started
• Intel FPGA Download Center
• Intel Arria 10 SX SoC Development Kit
• Intel FPGA Download Cable II
1.2. Signal Tap Tutorial Design Description
The design for this tutorial consists of the counter_50M 26-bit counter that counts to
49,999,999 and rolls over to 0.
For every 49,999,999 of counter_50M, counter_10 increases by 1 from 0 to 9 and
rolls over to 0.
792742 | 2024.02.15
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