XM25QH128AHIG-规格书-XMC(武汉新芯)NORFLASH规格书.PDF

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**XM25QH128AHIG规格书概述** XM25QH128AHIG是一款由武汉新芯（XMC）制造的128M-bit串行闪存（NOR Flash），专为各种电子设备提供非易失性存储解决方案。这款芯片具备高效能、低功耗和灵活的接口选项，适用于多种应用场合。 **关键特性** 1. **单电源操作**：工作电压范围为2.7到3.6伏，确保在不同电源环境下稳定运行。 2. **串行接口架构**：支持SPI兼容模式，包括Mode 0和Mode 3。提供了标准SPI、双SPI和四SPI接口，以适应不同的系统需求。此外，用户可配置虚周期数量。 3. **存储容量**：128M-bit的存储空间，等效于16,384 KByte或65,535个页面，每个编程页面为256字节。 4. **高性能读取**：正常读取速度高达50MHz，快速读取模式下，标准SPI、双SPI和四SPI分别可达104MHz，但需不同数量的虚周期。 5. **写入暂停与恢复**：支持写入暂停和恢复功能，允许在数据写入过程中中断并稍后继续，增强了系统的灵活性。 6. **SFDP（Serial Flash Discoverable Parameters）支持**：内建SFDP签名，方便系统自动识别和配置。 7. **低功耗设计**：典型活动电流仅为5mA，待机状态下典型电源下电流仅为1μA，有效降低能耗。 8. **统一的扇区结构**：采用4096个4-Kbyte扇区、512个32-Kbyte块和256个64-Kbyte块的结构，每个扇区或块可以独立擦除。 9. **软硬件写保护**：软件和硬件层面都支持全内存或部分内存的写保护，并可通过WP#引脚启用或禁用保护。 10. **软硬件复位**：提供软件和硬件复位功能，确保系统状态的可靠恢复。 11. **快速编程与擦除**：页编程时间为0.5ms，扇区擦除为40ms，半块擦除为200ms，块擦除为300ms，全芯片擦除为60秒。 12. **易用性**：包含可锁定的512字节OTP安全区域，用于存储敏感信息；可读取唯一的ID号码。 13. **耐久性和数据保留**：具有10万次的典型耐久性循环，数据保留时间长达20年。 14. **封装选项**：提供SOP 208mil 8L、WSON 5x6 8L和TFBGA 6x8 24ball等多种封装形式，所有封装均符合RoHS、无卤素和REACH标准。 15. **工作温度范围**：支持工业级温度范围，确保在各种环境条件下稳定工作。 XM25QH128AHIG是适用于嵌入式系统、物联网设备、微控制器和其它需要大容量、高性能非易失性存储的领域的理想选择。其丰富的特性集和高度的灵活性使其能够在多种应用场景中发挥重要作用。

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This Data Sheet may be revised by subsequent versions Wuhan Xinxin Semiconductor Manufacturing Corp.

or modifications due to changes in technical specifications.

XM25QH128A

preliminary

Rev. H, Issue Date: 2018/08/06

FEATURES

 Single power supply operation

- Full voltage range: 2.7-3.6 volt

 Serial Interface Architecture

- SPI Compatible: Mode 0 and Mode 3

 128 M-bit Serial Flash

- 128 M-bit / 16,384 KByte /65,535 pages

- 256 bytes per programmable page

 Standard, Dual or Quad SPI

- Standard SPI: CLK, CS#, DI, DO, WP#,

HOLD#/RESET#

- Dual SPI: CLK, CS#, DQ

, DQ

, WP#,

HOLD#/RESET#

- Quad SPI: CLK, CS#, DQ

, DQ

- Configurable dummy cycle number

 High performance

- Normal read

- 50MHz

- Fast read (Single Data Rate Mode)

- Standard SPI: 104MHz with 1 dummy bytes

- Dual SPI: 104MHz with 1 dummy bytes

- Quad SPI: 104MHz with 3 dummy bytes

 Write Suspend and Write Resume

 Support Serial Flash Discoverable

Parameters (SFDP) signature

 Low power consumption

- 5 mA typical active current

- 1A typical power down current

 Uniform Sector Architecture:

- 4096 sectors of 4-Kbyte

- 512 blocks of 32-Kbyte

- 256 blocks of 64-Kbyte

- Any sector or block can be erased individually

 Software and Hardware Write Protection:

- Write Protect all or portion of memory via

software

- Enable/Disable protection with WP# pin

 Software and Hardware Reset

 High performance program/erase speed

- Page program time: 0.5ms typical

- Sector erase time: 40ms typical

- Half Block erase time 200ms typical

- Block erase time 300ms typical

- Chip erase time: 60 Seconds typical

 Volatile Status Register Bits.

 Lockable 512 byte OTP security sector

 Read Unique ID Number

 Typical 100K endurance cycle

 Data retention time 20years

 Package Options

- SOP 208mil 8L

- WSON 5x6 8L

- TFBGA 6x8 24ball

- All Pb-free packages are compliant RoHS,

Halogen-Free and REACH.

 Industrial temperature Range

GENERAL DESCRIPTION

The XM25QH128A is a 128 Megabit (16,384K-byte) Serial Flash memory, with advanced write

protection mechanisms. The XM25QH128A supports the single bit and four bits serial input and output

commands via standard Serial Peripheral Interface (SPI) pins: Serial Clock, Chip Select, Serial DQ

(DI)

and DQ

(DO), DQ

(WP#) and DQ

(HOLD#/RESET#). SPI clock frequencies of up to 104Mhz are

supported allowing equivalent clock rates of 416Mhz(104Mhz x 4) for Quad Output while using the Quad

Output read instructions. The memory can be programmed 1 to 256 bytes at a time, using the Page

Program instruction.

The XM25QH128A also offers a sophisticated method for protecting individual blocks against erroneous

or malicious program and erase operations. By providing the ability to individually protect and unprotect

blocks, a system can unprotect a specific block to modify its contents while keeping the remaining

blocks of the memory array securely protected. This is useful in applications where program code is

patched or updated on a subroutine or module basis or in applications where data storage segments

need to be modified without running the risk of errant modifications to the program code segments.

The XM25QH128A is designed to allow either single Sector/Block at a time or full chip erase operation.

The XM25QH128A can be configured to protect part of the memory as the software protected mode.

The device can sustain a typical of 100K program/erase cycles on each sector or block.

XM25QH128A

128 Megabit 3V Serial Flash Memory with 4Kbyte Uniform Sector

This Data Sheet may be revised by subsequent versions Wuhan Xinxin Semiconductor Manufacturing Corp.

or modifications due to changes in technical specifications.

XM25QH128A

preliminary

Rev. H, Issue Date: 2018/08/06

SIGNAL DESCRIPTION

Serial Data Input, Output and IOs (DI, DO and DQ

, DQ

)

The XM25QH128A support standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions

use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the

rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to

read data or status from the device on the falling edge CLK.

Dual and Quad SPI instruction use the bidirectional IO pins to serially write instruction, addresses or

data to the device on the rising edge of CLK and read data or status from the device on the falling edge

of CLK.

Serial Clock (CLK)

The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See

SPI Mode")

Chip Select (CS#)

The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is

deselected and the Serial Data Output (DO, or DQ

, DQ

and DQ

) pins are at high impedance.

When deselected, the devices power consumption will be at standby levels unless an internal erase,

program or status register cycle is in progress. When CS# is brought low the device will be selected,

power consumption will increase to active levels and instructions can be written to and data read from

the device. After power-up, CS# must transition from high to low before a new instruction will be

accepted.

Write Protect (WP#)

The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in

conjunction with the Status Register’s Block Protect (SR.5, SR.4, SR.3, SR.2) bits and Status Register

Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The WP# function

is only available for standard SPI and Dual SPI operation, when during Quad SPI, this pin is the Serial

Data IO (DQ

) for Quad I/O operation.

HOLD (HOLD#)

The HOLD# pin allows the device to be paused while it is actively selected. When WXDIS bit is “0”

(factory default) and HRSW bit is ‘0’ (factory default is ‘0’), the HOLD# pin is enabled. When HOLD# is

brought low, while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins

will be ignored (don’t care). The hold function can be useful when multiple devices are sharing the same

SPI signals. The HOLD# function is only available for standard SPI and Dual SPI operation, when during

Quad SPI, this pin is the Serial Data IO (DQ

) for Quad I/O operation.

RESET (RESET#)

The RESET# pin allows the device to be reset by the controller. When WXDIS bit is “0” (factory default)

and HRSW bit is ‘1’ (factory default is ‘0’), the RESET# pin is enabled. The Hardware Reset function is

only available for standard SPI and Dual SPI operation, when during Quad SPI, this pin is the Serial

Data IO (DQ

) for Quad I/O operation. Set RESET# to low for a minimum period 1us (tHRST) will

interrupt any on-going instructions to have the device to initial state. The device can accept new

instructions again in 28us (tHRSL) after RESET# back to high.

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