01
Xilinx
0381219
456 3 2 1
REV
TITLE
SCHEM,ROHS COMPLIANT,ML555
PCIE PCI PCI-X PCB,1280389
SCALE SHEET
SIZE DWG NO
1236 5 4
B
A A
B
C
D
C
D
C
of
DRAWN BY
PCIe CEM Spec, Pg. 56 footnotes:
- By default the PETpx and PETnx pins shall be connected
to the PCI Express transmitter differential pair on the
system board, and the PCI Express receiver pair on the add-in card
- By default the PERpx and PERnx pins shall be connected
system board, and the PCI Express transmitter pair on the add-in card
to the PCI Express receiver differential pair on the
2) PCI Edge Connector P1 is keyed as 3.3V ONLY
ML555 PCB:
Notes:
1) Active Low Signals Names end in B or _B
3) +IOV for PCI edge connector is wired to 3.3V
4) Ref. Sheet 6:
Xilinx PCB Schematic Number: 0381219
Latest Schematics Revision:
ML555 Engineering Rev03 (3rd spin) will be
Production Rev01 for customer Release
Rev01_10-5-06
37
10-5-2006_15:48
1
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