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SLAS272F − JULY 2000 − REVISED JUNE 2004
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D Low Supply-Voltage Range, 1.8 V . . . 3.6 V
D Ultralow-Power Consumption:
− Active Mode: 280 µA at 1 MHz, 2.2V
− Standby Mode: 1.6 µA
− Off Mode (RAM Retention): 0.1 µA
D Five Power-Saving Modes
D Wake-Up From Standby Mode in less
than 6 µs
D 16-Bit RISC Architecture,
125-ns Instruction Cycle Time
D 12-Bit A/D Converter With Internal
Reference, Sample-and-Hold and Autoscan
Feature
D 16-Bit Timer_B With Seven
Capture/Compare-With-Shadow Registers
D 16-Bit Timer_A With Three
Capture/Compare Registers
D On-Chip Comparator
D Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
D Serial Communication Interface (USART),
Functions as Asynchronous UART or
Synchronous SPI Interface
− Two USARTs (USART0, USART1) —
MSP430x14x(1) Devices
− One USART (USART0) — MSP430x13x
Devices
D Family Members Include:
− MSP430F133:
8KB+256B Flash Memory,
256B RAM
− MSP430F135:
16KB+256B Flash Memory,
512B RAM
− MSP430F147, MSP430F1471
†
:
32KB+256B Flash Memory,
1KB RAM
− MSP430F148, MSP430F1481
†
:
48KB+256B Flash Memory,
2KB RAM
− MSP430F149, MSP430F1491
†
:
60KB+256B Flash Memory,
2KB RAM
D Available in 64-Pin Quad Flat Pack (QFP)
and 64-pin QFN
D For Complete Module Descriptions, See the
MSP430x1xx Family User’s Guide,
Literature Number SLAU049
†
The MSP430F14x1 devices are identical to the MSP430F14x
devices with the exception that the ADC12 module is not
implemented.
description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6 µs.
The MSP430x13x and the MSP430x14x(1) series are microcontroller configurations with two built-in 16-bit
timers, a fast 12-bit A/D converter (not implemented on the MSP430F14x1 devices), one or two universal serial
synchronous/asynchronous communication interfaces (USART), and 48 I/O pins.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and
process and transmit the data to a host system. The timers make the configurations ideal for industrial control
applications such as ripple counters, digital motor control, EE-meters, hand-held meters, etc. The hardware
multiplier enhances the performance and offers a broad code and hardware-compatible family solution.
Copyright 2000 − 2004, Texas Instruments Incorporated
!"# $"%&! '#(
'"! ! $#!! $# )# # # "#
'' *+( '"! $!#, '# #!#&+ !&"'#
#, && $##(
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SLAS272F − JULY 2000 − REVISED JUNE 2004
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
PLASTIC 64-PIN QFP
(PM)
PLASTIC 64-PIN QFP
(PAG)
PLASTIC 64-PIN QFN
(RTD)
−40°C to 85°C
MSP430F133IPM
MSP430F135IPM
MSP430F147IPM
MSP430F1471IPM
MSP430F148IPM
MSP430F1481IPM
MSP430F149IPM
MSP430F1491IPM
MSP430F133IPAG
MSP430F135IPAG
MSP430F147IPAG
MSP430F148IPAG
MSP430F149IPAG
MSP430F133IRTD
MSP430F135IRTD
MSP430F147IRTD
MSP430F1471IRTD
MSP430F148IRTD
MSP430F1481IRTD
MSP430F149IRTD
MSP430F1491IRTD
pin designation, MSP430F133, MSP430F135
17 18 19
P5.4/MCLK
P5.3
P5.2
P5.1
P5.0
P4.7/TBCLK
P4.6
P4.5
P4.4
P4.3
P4.2/TB2
P4.1/TB1
P4.0/TB0
P3.7
P3.6
P3.5/URXD0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DV
CC
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7
V
REF+
XIN
XOUT
Ve
REF+
V
REF−
/Ve
REF−
P1.0/TACLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
21 22 23 24
P5.6/ACLK
TDO/TDI
63 62 61 60 5964 58
AV
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
P2.6/ADC12CLK
P2.7/TA0
P3.0/STE0
P3.1/SIMO0
P1.7/TA2
P2.1/TAINCLK
P2.2/CAOUT/TA0
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/Rosc
56 55 5457
25 26 27 28 29
53 52
P1.5/TA0
XT2IN
XT2OUT
51 50 49
30 31 32
P3.2/SOMI0
P3.3/UCLK0
P3.4/UTXD0
P5.7/TBOUTH
TDI/TCLK
P5.5/SMCLK
AV
DV
PM, PAG, RTD PACKAGE
(TOP VIEW)
P1.6/TA1
P2.0/ACLK
CC
SS
SS
SLAS272F − JULY 2000 − REVISED JUNE 2004
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
pin designation, MSP430F147, MSP430F148, MSP430F149
17 18 19
P5.4/MCLK
P5.3/UCLK1
P5.2/SOMI1
P5.1/SIMO1
P5.0/STE1
P4.7/TBCLK
P4.6/TB6
P4.5/TB5
P4.4/TB4
P4.3/TB3
P4.2/TB2
P4.1/TB1
P4.0/TB0
P3.7/URXD1
P3.6/UTXD1
P3.5/URXD0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DV
CC
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7
V
REF+
XIN
XOUT
Ve
REF+
V
REF−
/Ve
REF−
P1.0/TACLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
21 22 23 24
P5.6/ACLK
TDO/TDI
63 62 61 60 5964 58
AV
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
P2.6/ADC12CLK
P2.7/TA0
P3.0/STE0
P3.1/SIMO0
P1.7/TA2
P2.1/TAINCLK
P2.2/CAOUT/TA0
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/Rosc
56 55 5457
25 26 27 28 29
53 52
P1.5/TA0
XT2IN
XT2OUT
51 50 49
30 31 32
P3.2/SOMI0
P3.3/UCLK0
P3.4/UTXD0
P5.7/TBOUTH
TDI/TCLK
P5.5/SMCLK
AV
DV
PM, PAG, RTD PACKAGE
(TOP VIEW)
P1.6/TA1
P2.0/ACLK
CC
SS
SS
SLAS272F − JULY 2000 − REVISED JUNE 2004
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
pin designation, MSP430F1471, MSP430F1481, MSP430F1491
17 18 19
P5.4/MCLK
P5.3/UCLK1
P5.2/SOMI1
P5.1/SIMO1
P5.0/STE1
P4.7/TBCLK
P4.6/TB6
P4.5/TB5
P4.4/TB4
P4.3/TB3
P4.2/TB2
P4.1/TB1
P4.0/TB0
P3.7/URXD1
P3.6/UTXD1
P3.5/URXD0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DV
CC
P6.3
P6.4
P6.5
P6.6
P6.7
Reserved
XIN
XOUT
DV
SS
DV
SS
P1.0/TACLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
21 22 23 24
P5.6/ACLK
TDO/TDI
63 62 61 60 5964 58
AV
P6.2
P6.1
P6.0
RST/NMI
TCK
TMS
P2.6
P2.7/TA0
P3.0/STE0
P3.1/SIMO0
P1.7/TA2
P2.1/TAINCLK
P2.2/CAOUT/TA0
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/Rosc
56 55 5457
25 26 27 28 29
53 52
P1.5/TA0
XT2IN
XT2OUT
51 50 49
30 31 32
P3.2/SOMI0
P3.3/UCLK0
P3.4/UTXD0
P5.7/TBOUTH
TDI/TCLK
P5.5/SMCLK
AV
DV
PM, RTD PACKAGE
(TOP VIEW)
P1.6/TA1
P2.0/ACLK
CC
SS
SS
SLAS272F − JULY 2000 − REVISED JUNE 2004
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagrams
MSP430x13x
Oscillator
ACLK
SMCLK
CPU
Incl. 16 Reg.
Bus
Conv
MCB
XIN XOUT P3 P4P2
XT2IN
XT2OUT
TMS
TCK
MDB, 16 Bit
MAB, 16 Bit
MCLK
4
TDI/TCLK
TDO/TDI
P5 P6
MAB,
4 Bit
DV
CC
DV
SS
AV
CC
AV
SS
RST/NMI
System
Clock
R
OSC
P1
16KB Flash
8KB Flash
512B RAM
256B RAM
ADC12
12-Bit
8 Channels
<10µs Conv.
Watchdog
Timer
15/16-Bit
Timer_B3
3 CC Reg
Shadow
Reg
Timer_A3
3 CC Reg
Test
JTAG
Emulation
Module
I/O Port 1/2
16 I/Os,
with
Interrupt
Capability
I/O Port 3/4
16 I/Os
POR Comparator
A
USART0
UART Mode
SPI Mode
I/O Port 5/6
16 I/Os
MDB, 8 Bit
MDB, 16-Bit
MAB, 16-Bit
8 8 8 8 8 8
MSP430x14x
Oscillator
ACLK
SMCLK
CPU
Incl. 16 Reg.
Bus
Conv
MCB
XIN XOUT P3 P4P2
XT2IN
XT2OUT
TMS
TCK
MDB, 16 Bit
MAB, 16 Bit
MCLK
4
TDI/TCLK
TDO/TDI
P5 P6
MAB,
4 Bit
DV
CC
DV
SS
AV
CC
AV
SS
RST/NMI
System
Clock
R
OSC
P1
Hardware
Multiplier
MPY, MPYS
MAC,MACS
60KB Flash
48KB Flash
32KB Flash
2KB RAM
2KB RAM
1KB RAM
ADC12
12-Bit
8 Channels
<10µs Conv.
Watchdog
Timer
15/16-Bit
Timer_B7
7 CC Reg
Shadow
Reg
Timer_A3
3 CC Reg
Test
JTAG
Emulation
Module
I/O Port 1/2
16 I/Os,
with
Interrupt
Capability
I/O Port 3/4
16 I/Os
POR Comparator
A
USART0
UART Mode
SPI Mode
USART1
UART Mode
SPI Mode
I/O Port 5/6
16 I/Os
MDB, 8 Bit
MDB, 16-Bit
MAB, 16-Bit
8 8 8 8 8 8
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