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1. General description
The LPC178x/7x is an ARM Cortex-M3 based microcontroller for embedded applications
requiring a high level of integration and low power dissipation.
The Cortex-M3 is a next generation core that offers better performance than the ARM7 at
the same clock rate and other system enhancements such as modernized debug features
and a higher level of support block integration. The Cortex-M3 CPU incorporates a
3-stage pipeline and has a Harvard architecture with separate local instruction and data
buses, as well as a third bus with slightly lower performance for peripherals. The
Cortex-M3 CPU also includes an internal prefetch unit that supports speculative
branches.
The LPC178x/7x adds a specialized flash memory accelerator to accomplish optimal
performance when executing code from flash. The LPC178x/7x is targeted to operate at
up to 100 MHz CPU frequency.
The peripheral complement of the LPC178x/7x includes up to 512 kB of flash program
memory, up to 96 kB of SRAM data memory, up to 4 kB of EEPROM data memory,
External Memory controller (EMC), LCD (LPC178x only), Ethernet, USB
Device/Host/OTG, a General Purpose DMA controller, five UARTs, three SSP controllers,
three I
2
C-bus interfaces, one eight-channel, 12-bit ADC, a 10-bit DAC, a Quadrature
Encoder Interface, four general purpose timers, two general purpose PWMs with six
outputs each, an ultra-low power RTC with separate battery supply, a windowed watchdog
timer, a CRC calculation engine, up to 165 general purpose I/O pins, and more. The
pinout of LPC178x/7x is intended to allow pin function compatibility with the LPC24xx and
LPC23xx.
2. Features and benefits
Functional replacement for LPC23xx and 24xx family devices.
System:
ARM Cortex-M3 processor, running at frequencies of up to 100 MHz. A Memory
Protection Unit (MPU) supporting eight regions is included.
ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
Multilayer AHB matrix interconnect provides a separate bus for each AHB master.
AHB masters include the CPU, and General Purpose DMA controller. This
interconnect provides communication with no arbitration delays unless two masters
attempt to access the same slave at the same time.
Split APB bus allows for higher throughput with fewer stalls between the CPU and
DMA. A single level of write buffering allows the CPU to continue without waiting for
completion of APB writes if the APB was not already busy.
LPC178x/7x
32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and
96 kB SRAM; USB Device/Host/OTG; Ethernet; LCD; EMC
Rev. 00.08 — 1 March 2011 Objective data sheet
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