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RMII转MII VHDL 文件代码PDF

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RMII转MII VHDL 文件代码，源码，可直接试用

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Reduced MII - MII Adapter- T. R. Arun Dec 18’97

National Semiconductor Confidential

page 1 of 21

Reduced MII

This document describes the implementation details of a RMII to MII Adapter.

Description:

The module translates RMII to MII on the receive side and translates MII to RMII on the transmit

side. The goal of this design is a). to support internal MII as well as an external MII and b). to

have a single clock domain. The internal MII refers to design where the translator design would

reside within a MAC like device while the external MII refers to an exposed MII like device. This

module also supports a mode in which the RMII mode can be bypassed individually for receive

and transmit.

Block Diagram:

crs_in

rxclk_in

rxd_in[3:0]

rxdv_in

rxer_in

col_in

rmii_crs

rmii_rxd[3:0]

rmii_rxdv

rmii_rxer

rmii_col

clk_50m

reset

speed_10

sel_rmiirx

f_duplex

async_mode

PDX_RX

crs_out

rxd_out[3:0]

rxclk_out

rxdv_out

rxer_out

col_out

txen_in

txer_in

rt_txen

rt_txer

rmii_txen

txen_out

txd_out[3:0]

txer_out

rmii_txer

rmii_txd[3:0]

txd_in[3:0] rt_txd

sel_rmiitx

PDX_TX rmii_txclk

txclk_out

txclk_in

Reduced MII - MII Adapter- T. R. Arun Dec 18’97

National Semiconductor Confidential

page 2 of 21

Receive RMII:

The purpose of the receive RMII is to translate RMII to MII signals for reception by a MAC like

device. The inputs, crs_in and rxd_in[1:0] are synchronous to clk_50m. The outputs, crs_out,

rxclk_out, rxd_out[3:0], rxdv_out, rxer_out and col_out are synchronous to clk_50m. The

outputs, rxd_out[3:0], rxdv_out and rxer_out are guaranteed to meet the setup and hold time

requirements with respect to rxclk_out.

Rx Block Diagram:

Start of receive activity is indicated by the asynchronous assertion of crs_in. The value of

rxd_in[1:0] is expected to be 2’h0 until a valid packet begins. The signal, begin_pkt, is asserted

once crs_in is true and rxd_in[1:0] is 2’h0 and deasserted when rxd_in[1:0] changes from 2’h0 to

2’h1 or 2’h2. The reason to look for zero on rxd_in is because, when in-band signalling is present

during Idle time between packets, the non-zero values are not interpreted as start of valid activity

as indicated in the following ﬁgure.

‘01’ and

‘10’ Detect

demux_sel

begin_pkt

st_fcs

end_fcs

rxd_in[1:0]

txen_in

speed_100

f_duplex

crs_in

crs_int

rxdv_int

non_zero

Rxclk Gen

rxd1[1:0]

nib_rxd[3:0]

nib_rxdv

nib_crs

nib_rxer

nib_col

rxclk_out

rxd_out[3:0]

rxdv_out

crs_out

rxer_out

col_out

clk_50m

reset

Reduced MII - MII Adapter- T. R. Arun Dec 18’97

National Semiconductor Confidential

page 3 of 21

The signal, non_zero, is asserted when rxd_in[1:0] changes from 2’h0 to 2’h1 or 2’h2. The

non_zero signal is used to generate a toggle pulse called demux_sel which toggles every clock in

100Mb or toggles every 10th clock in 10Mb. The incoming data is pipelined and captured on the

cycle when demux_sel is true. nib_rxdv is asserted when the data changes from 2’h0 to 2’h1,

while the deassertion is based on crs_in and demux_sel. nib_rxer is asserted when the data

changes from 2’h0 to 2’h2 and deasserted when rxd_in is no longer 2’h2. A receive error due to

decode error will not be recognized and so the MAC will compute the CRC for the packet to ﬂag

an error. nib_crs is asserted when crs_in goes true and is deasserted based on crs_in and

demux_sel.

Setting the async_mode means the crs_in is an asynchronous signal from the QuadPhyter and

hence a synchronizer is needed. The async_mode needs to be set for Rev 1 of QuadPhyter. For

usage with Rev 2 of QuadPhyter, the async_mode bit needs to be cleared.

The RX MII signals are all referenced to rxclk_out. The signals at the capture stage are then

retimed to guarantee the setup and hold time requirements on the RX MII. The retime ﬂops use

the rxclk_out as an enable.

Transmit RMII:

The purpose of the transmit RMII is to translate MII to RMII signals for reception by a PHY like

Tiruvur Arun, badge# M4531

Printed on Wed Dec 17 17:44:34 1997 Printed by DAI Signalscan DX 5.0.3 from Design Acceleration, Inc.

Group: Input

clk_50m = 1

crs_dv_in = 1

rxd_in[1:0] = ’h 1

Group: Debug

ss_crs = 1

rxd1[1:0] = ’h 0

begin_pkt = 1

non_zero = 0

non_zero_reg = 0

demux_sel = 0

nib_crs = 1

nib_rxclk = 1

nib_rxd[3:0] = ’h 0

nib_rxdv = 0

nib_rxer = 0

Group: Output

crs_out = 1

rxclk_out = 1

rxd_out[3:0] = ’h 0

rxdv_out = 0

rxer_out = 0

0 3 1 3 0 1

0 5

55,887.633 ns55,264.821 55,400 55,500 55,600 55,700

Cursor1 = 55,708 ns

Cursor2 = 55,742 ns

Reduced MII - MII Adapter- T. R. Arun Dec 18’97

National Semiconductor Confidential

page 4 of 21

device. The inputs, txen_in, txer_in and txd_in[1:0] are synchronous to txclk. The outputs,

txen_out, txer_out and txd_out[3:0] are synchronous to clk_50m.

There are two scenarios which need to be covered and guaranteed by design. The ﬁrst case is

where an external(or exposed) MII interface is involved. The txclk is normally an output from the

PHY’s CGM while the txen, txer and txd[3:0] are outputs from the MAC. These outputs are all

referenced to txclk. In this design, the txclk is derived from the clk_50m and fed to the MAC. The

output stage of the MAC will source the txen, txer and txd[3:0] based on txclk. These signals are

then retimed before it is fed into the MII-RMII translator. The retiming is necessary since the

delay of txen, txer and txd[3:0] from the rising edge of txclk can be in the range of 0 to 25ns. The

signals are then treated exactly as in an internal MII interface as described below.

The second case is where an internal MII interface is involved. The delay requirements are

spec’ed such that the turnaround delay from clk_50m to txclk to txd and txen into the translator is

not more than 12ns. The following diagram outlines a typical implementation.

The mux_sel, toggles every clock in 100Mb or every 10th clock in 10Mb and is cleared once txen

is deasserted. When mux_sel is low, the txd_out contains txd_in[1:0] and when mux_sel is high,

clk_50m

txclk

txd[3:0]

txen_in

mux_sel

1 2

1 - Clk to !Q + Inv = 3ns

2 - Clk tree delay + Clk to Q = 6.5ns

Clk Tree

txclk

txen_in, txd_in[3:0], txer_inData from Mac

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