Systemverilog+UVM搭建SOC

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svUVM搭建利用Systemverilog+UVM搭建SOC及ASIC的RTL验证环境
class ubus base test extends uvm testi uvm_ component utils(ubus base test 23456789 untable printer printer function new(string name="ubus base test", uvm component parent=null); super. new(name, parent endt unction 10 virtual function void build phaseuvm phase phase)i 11 super build phase(phase)i env-ubusenv:: type id:: create( "env", this)i 13 printer -new()i printer knobs. depth=3 567 endfunct ion task run phase(uvm phase phase); 18 super run phase (phase); uvm report info(get full name(),"start of test run phase.", UVM LOW) 20 21 endclass 1 define UBUS ADDR WIDTH 16 3 include " dut dummy Vl 4 include lubus if, sy 5 include "ubus pkg 6 module ubus tb top; 7 import uvm pkg:: *i 8 import ubus pkg:: *i include ntest lib. syl 10 1 ubus if if( 12 13 dut dummy dut 编译第一次通过 总结一:在一个芯片的验证平台中,总会给一个最baic的 base test,但是可能每个人 负责验证的部分是不一样的,比如说我要验证USB,那我一定会从 base test中派生一个 usb base test来给自己用,这样我可以在 usb base test加入任何我想要的函数,而不会影 响到其他人。 总结二:如何从test中传递参数到 top th,如果用 uvm config db在 base test中设置变 量的值,那么这些变量在 environment/agent/dirver等等中可以get到的,但是在 top th中 不能get到的?采用下面的方式就可以 uvm_config db #(int): :setnull, uvm_test top","set _usb_ _single-test", I); 总结三:需要注意的是,不要把定义 interface的文件 include在 package中,这会导致 编译不过的。 总结四: uvm report info和宏 uvm info在用法是没有区别的,都是用来打印消息的。 I-2]如何顺序的写UM平台(2) - MasterAgent 9.定义 sequence item,注意,一和类型的 transacton需要对应一个 driver; uvm object utils begin(ubus transfer) uvm field int (addr, UVM DEFAULT uvm field enum (ubus read write enum, read write, UVM DEFAULT) uvm field int (size, UVM DEFAULT uvm field array int(data, UVM DEFAULT uvm field array int(wait state UVM DEFAULT) uvm field int error pos, UVM DEFAULT) field int (transmit delay, UVM DEFAULT uvm field string (master, UVM DEFAULTJUVM NOCOMPARE uvm field string (slave, UVM DEFAULTJUVM NOCOMPARE uvm object utils end 4 1 typedef enum [NOP, READ, WRITE ubus read write enum 3 class ubus transfer extends uvm item and bit[15: 0 addr rand ubus read write enum read write: rand int unsigned size i rand bit[7: 0] data[ and bit [3: 0 wait state[l; rand int unsigned error pos i rand int unsigned transmit_delay=0; string slave=ln: constraint c read write[ ead write inside{READ,wR工T回} constraint size inside(1,2,4,8: 8901234 constraint c data wait size1 data size(==size; wait state size==size: constraint transmit delay t transimit- delay<-10: 678901 uvnobjcct_ utils begin(ubus transfer uvm field int(addr UVM DEFAULT uvm field enum(ubus read write enus, read write,UVM_DEFAULT uvm field int(size, UVM DEFAULT uvm_ int(data, UVM_ DEFAULT uvm field array int(wait state, UVM DEFAULT uvmfieldint (error_ pos, UVM_DEFAULT uvnfieldint(transmit delay, UVM_ DEFAULT uvm field string(master, UVM DEFAULT I UVM NOCOMPAREJ uvnfield string(slave, UVM_ DEFAULT UVM_NOCOMPARE) vm obiect utils end function new(string name=wubu transfer inst ")i 40 super.new(name)i infunction 42 coclass 需要思考哪些内容需要在 Lransaction中定义 10.定义好了 transaction,就可以开始定义 base sequence了;注意,在 base sequence的 pre body和 post body中定义 raise objection和 drop objection是很有好处的;将base equence定义成虚基类,只有派生后才能进行实例化 1 virtual class ubt s_base_sequence extends uvm sequence(ubus transfer) function new(string name="ubus_base_seg")i super. new(name); ndf unction //raise in pre_body so the objection is only raised for root. sequences //there is 0 need to raise for sub-sequences since the root sequence //will encapsulate the sub-sequence re body ( 12 uvm__type_name(),Setormatt(#%8 pre_ body ra Bing %8 objection", get_sequence_p ath(), starting phase. get_ name(),, UVM_MEDIUM); tarting_ pha se raise_objection( this)i endtask //drop the objection in the post body so the objection is removed when the root sequence omplctc virtual task post body 1 lif(starting_phase!=null, beg in info(get-type_name(),ssformatf("%s post_body () dropping %s abjection", get_sequen ce_path(), starting_phase. get_name starting_ phase. drop objection( this) end endtask 4 endclagg 11.派牛 sequence;先派牛出一个 sequence用于平台调试 26 class ready te_seq ext ends ubus_base_sequence Function new(string name="read byte_ seq")i infunction uvm_object_ utils(read byteseq) rand bit[15: c] start addr rand int unsigned transmit_del=0 constraint transmid del_ ct[(transmit_de1=101:] 7 virtual task body uvr do_with(req, [rea. addr==start addr; reg. read write==READi req. error⊥ps==1000 reg. transmit de lay==transmit de 2 get_ response(rsp): rinfoIget-type name(),ssformtf("s read: addr=x%Oh, data[01=x%0r,get_sequence_path anatase 47 endclass 12.用了 scqucncc,就该写 scqucnccr了; scqucnccT是整个环境中最简单的部分 1 class ubus_ master_ sequencer extends uvm sequencer #(ubus transter); 2 uvm-component_utils(ubusnaster_sequencer) funct=on new (string name, uvm component parent) super. new(name, parent) 6 erid uric L⊥r 8 endclass 13.有∫ sequencer,就可以定义 driver了,定义好 driver,然后需要在 agent中进行例化 在 driver中一定要 get interface,因为 driver直接和DUT做交互 6 I class ubus_ master driver extends tvm driver #(ubus-rarsfer): 2345678 protected virtual ub fvi三 protected int master_; uVIlL-CoiLponler: L_uTils beg in(ubls_rlas Ler_driver uvI field int (master id, UVE DEFAULT vm componert_ utils_end 10 Function new(string name, uvm_component parent); super. new(name, parent); 111111 endfunction Function void build phasc(uvm _phasc phasc)i super build phase(phase) i f( llvm conf ig_ab#(virtual ubus_if)::get(this, "", "vif", vif) 18 endfunct, uvm fatal("No vif,I"virtual interface must be set for: ",get full- name(),"vis l4.注意在 driver中如何写 get sequence: irtual protected task get anc drive() 28 @( egede v⊥「, sigLe8eL); 29 forever begin 30 (posedge vif. sig_clock 31 segitem port get_ next item(reg)i 32 scast(rsp, reg. clone()) 33 rsp. set_ id info(req)i 34 drive transfer(rsp)i 35 segitem port item_dore()i 36 seq_item _port. put_response(rsp)i 37 end 38 endtask 15.有了 scqucnccr, drivcr,实际上就可以定义 master agent了,在 agent巾要实现 direr和 的连接 1 class ubus ma ster agent extends uvm agenti 2 protected -rt master_id: ubus master driverdriver 5 uvm_sequencer (bus transfer) se: 8 rm tield int(master id, UVM DEFAULT) uvm_component utils_ena function new(string name, uvm component carent)i super. new (name, paver)i endfnction unction build phase (uvm phaae phase) super build phase(phase): (get is active(i==UVM ACTIvE) begin 19 squencer=uvm sequencer (ubus tramsfer):: yce id: :create["sequencer", this)i driver=ubus_ master driver:: type_id: create("driver", this) endfinction function void connect_ _phase(uvm phasephase: f(get_is active()==UVM_ ACTIvE) beg ia driver seq i le pcxr t. connec:t (secl enc: er. sec-Leinexpor L) 29 endless 16. Agent实现∫之后,就需要在env中例化 1 class ubus env ex tends uvm envi protected virtual interf ace ubus //uvm_component_utils(ubu s_env) protected int num masters=0 bua master agent masters[l; uvm_component_utils begin(ubus_env) uvn[ int (num ma sters, UVM DEFAULT) uvm component utils end function new( string name, uvm component parent) super, new(name, parent ndfuncticl function void build_phasc (uvm_phascphasc) string lng_ name i if (luvmcon=ig__db#(virtual ubus_if:: get(this, "i, "vif", vif)) uvmfacal("No vif",I"virtual interface must be set for: " get ful name(),"vif"]) void(uvm config_db#(int):: cet(this, "","num masters", num masters)); masters-nlew [num masters]i for(int 1=0 num masters: 1++ begin ssf ormat(inst name,"masters [%od]"r i masters[i]=ubus master agent:: type_ id: create(inst_ name, this,: vOid(uvm config_ dh#(int)::set(this, (inst_name,"driver"),"master-a d endfuncticn 32endc1a器a 17.然后更改 test lib. sy,写一个从 basc test派生出来的tcst,设置默认的 scqucncc和 master 的数量; 25 class test read byte extends ubus base testi t utils(tcst rcad byte) function ncw(string namc=tcst rcad byte, uvm component parent=null)i 30 super ncw(namc, parent)i infunction 33 virtual function void buile phase(uvm phasephase eg r uvm_config_abt(int):: set(this, "env","num_ masters",1): 36 uvm_config ab#(uvm object wrapper):: set( this, wenv masters [ol, se quenc. phase","default_sequencea, read byte_seg:: type_id:: get() super build phase(phase)i naf unction 40 endless 18.然后在 ubus pkg. SV中 include各个 component的文件,然后编译,修改一些语法错误 但是一直会出现如下错误: make test read byte irun-access rw-uvmhome /home/dengf/uvm-1.1 +UVM_VERBOSITY=UVM_LOw-quiet +define+UVM_OBJECT MUST_HAVE_CONSTRUCTOR -indir. ubus_tb_top. sv +UVM_TESTNAME=test_read_byte uvm config db#(uvm object wrapper):: set(this, env. masterson, sequencer, run phase "default_sequence",read_byte_seq: type_id:: get()): uvm_config._dbf#(uvm_o bject_wrapper); /'s read_byte_seq could not be bound " default_sequence", read_byte_seq: type_id: get(/ t(this, "env. masters[01.sequencer, run_phase ncvlog: *E, NOTFXX (test lib, Sv, 36139): Expecting a function name [10,3.3(IEEE) irun: *E, VLGERR: An crror occurred during parsing, Revicw the log file for crrors with the co de*E and fix those identified problems to proceed. Exiting with code (status 1) make: *** [read byte] Error 1 19.错误的意思是说这个 sequence不能够get到,在屏蔽掉设置默认的 sequence后,编译 可以正确的通过,但是此时平台中没有数据的流动,需要 debug clagg test_read byte extends ubus_base_test 26 t_utils(test_read byte) 29 function new(string name="test read byte", uvm_ component parent=null surer. new(name, parent): 31 end=unction virtual function void build phase(uvm phasephase): 34 uvm_config_ db#(int):: set(this, "env","rum masters", 1) 3 n-phase","o"/ uvn conf ig_dbt(uv_object_wrapper): : se:(this,"env. masters [O]. sequencer.r 36 fault_sequence", read byte seg:: type-2:: get()); superbu (p ase) infunction 40 andalas冒 20.打开上面的屏蔽,到 read byte seq中去,将 task body屏蔽掉也可以pass rand bit [15: 0 start acdr; nd int uns:gned transmit del=0 constraint transmid del ctfftransmit_del<=10):) virtual task hady () mmreport_info(get_full_name(),"sequence iB okay now, please FIXME.\n", UVM_IONE); uvm_do_with(req adar==start addr: ac write-READ egerror pos== 1000; reg-traramit delay==cranamit-_del: info(get-typo-name!), Isp. dd La [o]), UVT HIGH) endtask 21.到目前为止,该平台中有ENV, agent, driver, sequencer, sequence, transaction了 可以进行最基本的tst操作了,但是还需要 monitor, scoreboard等等 总结一: driver( sequencer是)是和发送的 sequence类型有关的,也就是一个 driver 要发送的 sequence的类型是固定死了的,那么我们需要将多种类型的 sequence通 过一个 driver来发送要怎么办?其实将多种类型的 scqucncc不要做成 scqucncc,做 成 uvm object,然后在个大的 uvm object中 rando这些小的 uvm object(就是 小的 sequence),然后用这个最人的 uvm object来做 sequence item就对了。 总结二: sequence item中要具备哪些内容呢?严格的说是你当前 module所要用到的所 用 data flow的数据类型 总结三:别忘记在 driver中 get interface 1-3如何顺序的写UVM平台(3) Master monitor 22.编写 master monitor;该 component的主要作用是收集 driver发出的各种数据类型的 coverage。然后需要在 agent中例化 component_ utils begin (ubus master monitor UVM DEFAULT uvm int(checks enable, UVM DEFAULT eld int(c rage_enable, UVM DEFAULT uvcomponent_ utils_end function new string name, uvm component parent) (name, parent); cov_ trans. set inst name((get full name(), ".cov trans"))i 5 cov trans beat set inst name(ige: full name (),". cov trans beat.1)i trans collected-new()i 55 icem. port=new("item_ collected_port",thisi endfunction 58 function void build phase(uvm phase pha se); i=(Iuvm_ dbt(virtual ubuB it)::get(thig, r vit vif)) fatal("no vif",("virtual interface must be set for get_full_name(),"vifm); infunction 23.在 agent中对 master的 monitor进行例化之后, master的部分就已经完成; uvcomponent_ utils begin(ubus master moni tor) 43 vmfieldint(master_id, UVM_DEFAULT uvm field int( checks enable, UVM DEFAULT uvmfieldint (coverage_enable, UVM_DEFAULT) 46 VIT_component_utils_end 4 tunction new string name, uvm_ component parent): 49 super. new(name, parent)i ov transnet covtrans set_inst name((get_ name),"cov trans) 52 COV ov trans beat set inst name(iget full name ()," cov trans beat): trans coIlected=new(: 5 icem collected por t-new("item collected port", this): endtunction function void build phase(uvm phasephase): super, buld__phase(phase) if(Iuvm_config_db(virtual ubus_if):: get(this, m", "vif", vif)) uvm fatal("no vif",["virtual interface muat be set Eo: r get full name(),",viE"1)i 24.到目前为止,平台能动,但是没有 sequence在里面流动,所以时间是没有动的;需要 在日前现有的资源下解决这个问题?这是因为在 sequence中没有打开 uvm do*相关的 函数;打开后时钟就开始动了,但是停止不下米,需要进一步 debug virtual task body ( uvm_report_info iget_full- nane(),"sequence is okay now, please FIXME. n", UVM_NONE I; undo (reg) uvm do with(reg irec addr=-start addr write==READ: error pos== 1000; C. 0e/ reg transmit_delay=transmit_celi rfo(get-type_name () Ssformtf("%s read: adar=x%oh, data [o]='x8Oh, get_sequence_path(),Isp addr edtas 5D endless 25.如何让平台停止下来呢?不能够停止是因为有一根信号没有驱动,导致一直等待 L「「凵「L「「 addr[ 15:01 us size[1: 0] animas zzz00012 3号343号3号3 3mta[7:0 士sHt 10

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试读 50P Systemverilog+UVM搭建SOC
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cs824980820 比较基础,还是值得看一下
2021-01-26
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验师 值得再次回味~
2019-08-18
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sunbox98 初看挺实用,期待进一步阅读
2019-04-27
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