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JEDEC Standard No. 21-C
Page 4.1.2.11 – 1
Annex K: Serial Presence Detect (SPD) for DDR3 SDRAM Modules
DDR3 SPD
Document Release 5
UDIMM Revision 1.2RDIMM Revision 1.2CDIMM Revision 1.2LRDIMM Revision 1.11.0
Introduction
This annex describes the serial presence detect (SPD) values for all DDR3 modules.
Differences between module typesare encapsulated in subsections of this annex. These
presence detect values are those referenced in the SPD standarddocument for ‘Specific
Features’. The following SPD fields will be documented in the order presented in
section 1.1 withthe exception of bytes 60 ~ 116 which are documented in separate
appendices, one for each family of module types.Further description of Byte 2 is found
in annex A of the SPD standard. All unused entries will be coded as 0x00. Allunused
bits in defined bytes will be coded as 0 except where noted.
To allow for maximum flexibility as devices evolve, SPD fields described in this
document may support device configura-tion and timing options that are not included in
the JEDEC DDR3 SDRAM data sheet (JESD79-3). Please refer to DRAMsupplier data sheets or
JESD79-3 to determine the compatibility of components.
1.1 Address map
The following is the SPD address map for all DDR3 modules. It describes where the
individual lookup table entries will beheld in the serial EEPROM.
Byte Number
0123456789101112131415161.2.3.4.
Function Described
Number of Serial PD Bytes Written / SPD Device Size / CRC CoverageSPD Revision
Key Byte / DRAM Device TypeKey Byte / Module TypeSDRAM Density and BanksSDRAM
Addressing
Module Nominal Voltage, VDDModule OrganizationModule Memory Bus Width
Fine Timebase (FTB) Dividend/DivisorMedium Timebase (MTB) DividendMedium Timebase (MTB)
DivisorSDRAM Minimum Cycle Time (tCKmin)Reserved
CAS Latencies Supported, Least Significant ByteCAS Latencies Supported, Most
Significant ByteMinimum CAS Latency Time (tAAmin)
3333333Notes1, 2
Number of SPD bytes written will typically be programmed as 128 or 176 bytes.Size of
SPD device will typically be programmed as 256 bytes.From DDR3 SDRAM datasheet.
These are optional, in accordance with the JEDEC spec.
Release 22
JEDEC Standard No. 21-CPage 4.1.2.11 – 2
Byte Number
Function Described
Notes17Minimum Write Recovery Time (tWRmin)318Minimum RAS# to CAS# Delay Time (tRCDmin)
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