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TPS54202 4.5V 至 28V 输入、2A 输出、EMI 友好型同步降压转换器
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TPS54202 4.5V 至 28V 输入、2A 输出、EMI 友好型同步降压转换器 详细的计算过程
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TPS54202 4.5-V to 28-V Input, 2-A Output, EMI Friendly
Synchronous Step Down Converter
1 Features
• 4.5-V to 28-V wide input voltage range
• Integrated 148-mΩ and 78-mΩ MOSFETs for 2-A,
continuous output current
• Low 2-μA shutdown, 45-μA quiescent current
• Internal 5-mS soft start
• Fixed 500-kHz switching frequency
• Frequency spread spectrum to reduce EMI
• Advanced Eco-mode
™
pulse skip
• Peak current mode control
• Internal loop compensation
• Overcurrent protection for both MOSFETs with
hiccup mode protection
• Overvoltage protection
• Thermal shutdown
• SOT-23 (6) package
2 Applications
• 12-V, 24-V distributed power-bus supply
• Industry application
– White goods
• Consumer application
– Audio
– STB, DTV
– Printer
3 Description
The TPS54202 is a 4.5-V to 28-V input voltage
range, 2-A synchronous buck converter. The device
includes two integrated switching FETs, internal loop
compensation and 5-ms internal soft start to reduce
component count.
By integrating the MOSFETs and employing the
SOT-23 package, the TPS54202 achieves the high
power density and offers a small footprint on the PCB.
Advanced Eco-mode implementation maximizes the
light load efficiency and reduces the power loss.
The frequency spread spectrum operation is
introduced for EMI reduction.
Cycle-by-cycle current limit in both high-side MOSFET
protects the converter in an overload condition and
is enhanced by a low-side MOSFET freewheeling
current limit which prevents current runaway. Hiccup
mode protection is triggered if the overcurrent
condition has persisted for longer than the present
time.
Device Information
PART NUMBER PACKAGE
(1)
BODY SIZE (NOM)
TPS54202 SOT-23 (6) 1.60 mm × 2.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
VIN
EN
GND
BOOT
FB
SW
VIN
VOUT
EN
Cin
Lo
Rfb1
Rfb2
Co
Cboot
3
1
5
2
4
6
TPS54202
Copyright © 2016, Texas Instruments Incorporated
Simplified Schematic
Output Current (A)
Efficiency (%)
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1
D100
V
IN
= 12 V, V
OUT
= 5 V
V
IN
= 12 V, V
OUT
= 3.3 V
V
IN
= 24 V, V
OUT
= 5 V
V
IN
= 24 V, V
OUT
= 3.3 V
Efficiency vs Output Current
www.ti.com
TPS54202
SLVSD26B – APRIL 2016 – REVISED APRIL 2021
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
1
Product Folder Links: TPS54202
TPS54202
SLVSD26B – APRIL 2016 – REVISED APRIL 2021
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Timing Requirements.................................................. 5
7 Detailed Description........................................................8
7.1 Overview..................................................................... 8
7.2 Functional Block Diagram........................................... 8
7.3 Feature Description.....................................................9
7.4 Device Functional Modes..........................................12
8 Application and Implementation.................................. 13
8.1 Application Information............................................. 13
8.2 Typical Application.................................................... 13
9 Power Supply Recommendations................................20
10 Layout...........................................................................21
10.1 Layout Guidelines................................................... 21
10.2 Layout Example...................................................... 21
11 Device and Documentation Support..........................22
11.1 Device Support........................................................22
11.2 Receiving Notification of Documentation Updates.. 22
11.3 Support Resources................................................. 22
11.4 Trademarks............................................................. 22
11.5 Electrostatic Discharge Caution.............................. 22
11.6 Glossary.................................................................. 22
12 Mechanical, Packaging, and Orderable
Information.................................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (January 2017) to Revision B (April 2021) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document. ................1
• Changed the max centre switching frequency from 590 kHz to 630 kHz........................................................... 5
• Changed the max low-side source current limit from 4 A to 4.3 A......................................................................5
Changes from Revision * (April 2016) to Revision A (January 2017) Page
• Changed R1 to R4 in Equation 2 ....................................................................................................................... 9
• Changed Section 7.3.11.2 ................................................................................................................................11
• Added Figure 7-3 ............................................................................................................................................. 12
• Added Note 1 to Table 8-2 ............................................................................................................................... 17
TPS54202
SLVSD26B – APRIL 2016 – REVISED APRIL 2021
www.ti.com
2 Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54202
5 Pin Configuration and Functions
1GND 6 BOOT
2SW 5 EN
3VIN 4 FB
Figure 5-1. 6-Pin SOT-23 DDC Package (Top View)
Table 5-1. Pin Functions
PIN
TYPE
(1)
DESCRIPTION
NAME NO.
BOOT 6 O
Supply input for the high-side NFET gate drive circuit. Connect a 0.1-μF capacitor between BOOT and
SW pins.
EN 5 I This pin is the enable pin. Float the EN pin to enable.
FB 4 I Converter feedback input. Connect to output voltage with feedback resistor divider.
GND 1 –
Ground pin. Source terminal of low-side power NFET as well as the ground terminal for controller circuit.
Connect sensitive VFB to this GND at a single point.
SW 2 O Switch node connection between high-side NFET and low-side NFET.
VIN 3 – Input voltage supply pin. The drain terminal of high-side power NFET.
(1) O = Output; I = Input
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TPS54202
SLVSD26B – APRIL 2016 – REVISED APRIL 2021
Copyright © 2021 Texas Instruments Incorporated
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3
Product Folder Links: TPS54202
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN MAX UNIT
Input voltage range, V
I
VIN –0.3 30 V
EN –0.3 7 V
FB –0.3 7 V
Output voltage range, V
O
BOOT-SW –0.3 7 V
SW –0.3 30 V
SW (20 ns transient) –5 30 V
Operating junction temperature, T
J
–40 150 °C
Storage temperature range, T
stg
–65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE UNIT
V
(ESD)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±4000
V
Charged-device model (CDM), per JEDEC specification JESD22-C101
(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
I
Input voltage range
VIN 4.5 28 V
EN –0.1 7 V
FB –0.1 7 V
V
O
Output voltage range
BOOT-SW –0.1 7 V
SW –0.1 28 V
T
J
Operating junction temperature –40 125 °C
6.4 Thermal Information
THERMAL METRIC
(1)
TPS54202
UNITDDC ( SOT23)
6 PINS
R
θJA
Junction-to-ambient thermal resistance 89.2 °C/W
R
θJC(top)
Junction-to-case (top) thermal resistance 39.5 °C/W
R
θJB
Junction-to-board thermal resistance 14.7 °C/W
ψ
JT
Junction-to-top characterization parameter 1.2 °C/W
ψ
JB
Junction-to-board characterization parameter 14.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, .
TPS54202
SLVSD26B – APRIL 2016 – REVISED APRIL 2021
www.ti.com
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Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54202
6.5 Electrical Characteristics
The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These
specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life
of the product containing it. T
J
= –40°C to +125°C, V
IN
= 4.5 V to 28 V, (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY
V
IN
Input voltage range 4.5 28 V
I
Q
Non switching quiescent current EN =5 V, VFB = 1 V 45 µA
I
OFF
Shut down current EN = GND 2 µA
V
IN(UVLO)
VIN under voltage lockout
Rising V
IN
3.9 4.2 4.4 V
Falling V
IN
3.4 3.7 3.9 V
Hysteresis 400 480 560 mV
ENABLE (EN PIN)
V
(EN_RISING)
Enable threshold
Rising 1.21 1.28 V
V
(EN_FALLING)
Falling 1.1 1.19 V
I
(EN_INPUT)
Input current V
EN
= 1 V 0.7 μA
I
(EN_HYS)
Hysteresis current V
EN
= 1.5 V 1.55 μA
FEEDBACK AND ERROR AMPLIFIER
V
FB
Feedback Voltage V
IN
= 12 V 0.581 0.596 0.611 V
PULSE SKIP MODE
I
(SKIP)
(1)
Pulse skip mode peak inductor current threshold V
IN
= 24 V, V
OUT
= 5 V, L = 15 µH 300 mA
POWER STAGE
R
(HSD)
High-side FET on resistance T
A
= 25°C, V
BST
– SW = 6 V 148 mΩ
R
(LSD)
Low-side FET on resistance T
A
= 25°C, V
IN
= 12 78 mΩ
CURRENT LIMIT
I
(LIM_HS)
High side current limit 2.5 3.2 3.9 A
I
(LIM_LS)
Low side source current limit 2 3 4.3 A
OSCILLATOR
F
sw
Centre switching frequency 390 500 630 kHz
OVER TEMPERATURE PROTECTION
Thermal
Shutdown
(1)
Rising temperature 155 °C
Hysteresis 10 °C
Hiccup time 32768 Cycles
(1) Not production tested
6.6 Timing Requirements
MIN
TYP MAX UNIT
OVER CURRENT PROTECTION
t
HIC_WAIT
Hiccup up wait time 512 Cycles
t
HIC_RESTART
Hiccup up time before restart 16384 Cycles
t
SS
Soft-start time 5 mS
ON TIME CONTROL
t
MIN_ON
(1)
Minimum on time, measured at 90% to 90% and 1-A loading 110 ns
www.ti.com
TPS54202
SLVSD26B – APRIL 2016 – REVISED APRIL 2021
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: TPS54202
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