DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final 1
Version: DM9000-DS-F03
April 23, 2009
1. General Description
The DM9000 is a fully integrated and cost-effective
single chip Fast Ethernet MAC controller with a
general processor interface, a 10/100M PHY and 4K
Dword SRAM. It is designed with low power and high
performance process that support 3.3V with 5V
tolerance.
The DM9000 also provides a MII interface to connect
HPNA device or other transceivers that support MII
interface. The DM9000 supports 8-bit, 16-bit and
32-bit uP interfaces to internal memory accesses for
different processors. The PHY of the DM9000 can
interface to the UTP3, 4, 5 in 10Base-T and UTP5 in
100Base-TX. It is fully compliant with the IEEE 802.3u Spec.
Its auto-negotiation function will automatically configure the
DM9000 to take the maximum advantage of its abilities. The
DM9000 also supports IEEE 802.3x full- duplex flow control.
This programming of the DM9000 is very simple, so user
can port the software drivers to any system easily.
2. Block Diagram
EEPROM
Interface
External MII
Interface
LED
TX+/-
RX+/-
MII Management
Control
& MII Register
Autonegotiation
Memory
Management
RX Machine
TX Machine
MAC
MII
100 Base-TX
PCS
100 Base-TX
transceiver
10 Base-T
Tx/Rx
PHYceiver
Control &Status
Registers
Internal
SRAM
Processor
Interface
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final 2
Version: DM9000-DS-F03
April 23, 2009
Table of Contents
1. General Description.............................................. 1
2. Block Diagram……………………………………… 1
3. Features................................................................4
4. Pin Configuration ..................................................5
4.1 Pin Configuration I: with MII Interface ................5
4.2 Pin Configuration II: with 32-Bit Data Bus ..........6
5. Pin Description .....................................................7
5.1 MII Interface........................................................ 7
5.2 Processor Interface ............................................8
5.3 EEPROM Interface. ............................................9
5.4 Clock Interface.................................................... 9
5.5 LED Interface......................................................9
5.6 10/100 PHY ......................................................10
5.7 Miscellaneous Pins...........................................10
5.8 Power Pins ....................................................... 10
6. Vendor Control and Status Register Set............. 11
6.1 Network Control Register (00H) .......................13
6.2 Network Status Register (01H).........................13
6.3 TX Control Register (02H) ................................13
6.4 TX Status Register I (03H)................................14
6.5 TX Status Register II (04H)...............................14
6.6 RX Control Register (05H)................................14
6.7 RX Status Register (06H) .................................15
6.8 Receive Overflow Counter Register (07H) .......15
6.9 Back Pressure Threshold Register (08H).........15
6.10 Flow Control Threshold Register (09H)..........16
6.11 RX/TX Flow Control Register (0AH) ...............16
6.12 EEPROM & PHY Control Register (0BH).......16
6.13 ROM & PHY Address Register (0CH) ............17
6.14 EEPROM & PHY Data Register (0DH, 0EH) .17
6.15 Wake Up Control Register (0FH)....................17
6.16 Physical Address Register (10H~15H)........... 17
6.17 Multicast Address Register (16H~1DH) .........18
6.18 General Purpose Control Register (1EH)…….18
6.19 General Purpose Register (1FH)....................18
6.20 TX SRAM Read Pointer Address Register
(22H~23H) ..............................................................18
6.21 RX SRAM Write Pointer Address Register
(24H~25H).......................................................19
6.22 Vendor ID Register (28H~29H) ......................19
6.23 Product ID Register (2AH~2BH).....................19
6.24 Chip Revision Register (2CH) ........................19
6.25 Special Mode Control Register (2FH).............19
6.26 Memory Data Read Command without Address
Increment Register (F0H)................................19
6.27 Memory Data Read Command with Address
Increment Register (F2H)................................19
6.28 Memory Data Read_ address Register
(F4H~F5H) .....................................................19
6.29 Memory Data Write Command without Address
Increment Register (F6H)................................19
6.30 Memory Data Write Command with Address
Increment Register (F8H)................................19
6.31 Memory Data Write_ address Register
(FAH~FBH)......................................................20
6.32 TX Packet Length Register (FCH~FDH) ........20
6.33 Interrupt Status Register (FEH) ......................20
6.34 Interrupt Mask Register (FFH)........................20
7. EEPROM Format................................................21
8. MII Register Description .....................................22
8.1 Basic Mode Control Register (BMCR) – 00......23
8.2 Basic Mode Status Register (BMSR) – 01 .......24
8.3 PHY ID Identifier Register #1 (PHYID1) – 02... 25
8.4 PHY Identifier Register #2 (PHYID2) – 03 .......25
8.5 Auto-negotiation Advertisement Register
(ANAR) – 04 ....................................................26
8.6 Auto-negotiation Link Partner Ability Register
(ANLPAR) – 05................................................27
8.7 Auto-negotiation Expansion Register (ANER) – 06
.........................................................................27
8.8 DAVICOM Specified Configuration Register
(DSCR) – 16..................................................... 28
8.9 DAVICOM Specified Configuration and Status
Register (DSCSR) – 17 ...................................29
8.10 10BASE-T Configuration/Status (10BTCSR) – 18
.........................................................................30
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final 3
Version: DM9000-DS-F03
April 23, 2009
9. Functional Description........................................ 31
9.1 Host Interface ...................................................31
9.2 Direct Memory Access Control .........................31
9.3 Packet Transmission ........................................31
9.4 Packet Reception ............................................. 31
9.5 100Base-TX Operation.....................................32
9.5.1 4B5B Encoder ...............................................32
9.5.2 Scrambler ......................................................32
9.5.3 Parallel to Serial Converter............................32
9.5.4 NRZ to NRZI Encoder ...................................32
9.5.5 MLT-3 Converter............................................32
9.5.6 MLT-3 Driver .................................................. 32
9.5.7 4B5B Code Group .........................................33
9.6 100Base-TX Receiver ......................................34
9.6.1 Signal Detect ................................................. 34
9.6.2 Adaptive Equalization ....................................34
9.6.3 MLT-3 to NRZI Decoder.................................34
9.6.4 Clock Recovery Module................................. 34
9.6.5 NRZI to NRZ..................................................34
9.6.6 Serial to Parallel ............................................34
9.6.7 Descrambler ..................................................34
9.6.8 Code Group Alignment .................................. 35
9.6.9 4B5B Decoder ...............................................35
9.7 10Base-T Operation .........................................35
9.8 Collision Detection............................................35
9.9 Carrier Sense ................................................... 35
9.10 Auto-Negotiation .............................................35
9.11 Power Reduced Mode ....................................36
9.11.1 Power Down Mode ......................................36
9.11.2 Reduced Transmit Power Mode ..................36
10. DC and AC Electrical Characteristics ...............37
10.1 Absolute Maximum Rating (25∘C) ................37
10.2 Operating Conditions......................................37
10.3 DC Electrical Characteristics..........................38
10.4 AC Electrical Characteristics & Timing
Waveforms ...................................................... 39
10.4.1 TP Interface .................................................39
10.4.2 Oscillator/ Crystal Timing.............................39
10.4.3 Processor Register Read Timing.................39
10.4.4 Processor Register Write Timing................. 40
10.4.5 External MII Interface Transmit Timing........41
10.4.6 External MII Interface Receive Timing.........41
10.4.7 MII Management Interface Timing............... 42
10.4.8 EEPROM Interface Timing ..........................42
11. Application Notes ..............................................43
11.1 Network Interface Signal Routing ................... 43
11.2 10Base-T/100Base-TX Application Figure 11-1
.........................................................................43
11.3 10Base-T/100Base-TX (Power Reduction
Application) Figure 11-2................................44
11.4 Power Decoupling Capacitors Figure 11-3 .....45
11.5 Ground Plane Layout Figure 11-4...................46
11.6 Power Plane Partitioning Figure 11-5 .............47
11.7 Magnetics Selection Guide .............................48
11.8 Crystal Selection Guide Figure 11-6 ...............48
11.9 Application of reverse MII Figure 11-7 ............49
12. Package Information.........................................50
12.1 LQFP 100L Outline Dimensions .....................50
13. Appendix ...........................................................51
14. Order Information .............................................53
3. Features
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final 4
Version: DM9000-DS-F03
April 23, 2009
■ Supports processor interface: byte/word/dword of
I/O command to internal memory data operation
■ Integrated 10/100M transceiver
■ Supports MII and reverses MII interface
■ Supports back pressure mode for half-duplex
mode flow control
■ IEEE802.3x flow control for full-duplex mode
■ Supports wakeup frame, link status change and
magic packet events for remote wake up
■ Integrated 4K dword SRAM
■ Supports automatically load vendor ID and
product ID from EEPROM
■ Supports 4 GPIO pins
■ Optional EEPROM configuration
■ Very low power consumption mode:
– Power reduced mode (cable detection)
– Power down mode
– Selectable TX drivers for 1:1 or 1.25:1
transformers for additional power reduction.
■ Compatible with 3.3V and 5.0V tolerant I/O
■ 100-pin LQFP with CMOS process
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final 5
Version: DM9000-DS-F03
April 23, 2009
4. Pin Configuration
4.1 Pin Configuration I: with MII Interface
11
DM9000
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56 (I)
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
76
TXD1
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
BGRES
DGND
NC
LINK_O
WAKEUP
PW_RST#
DGND
SD12
IOR#
77
78
79
80
81
82
83
84
85
SD15
SD14
SD13
SD8
SD11
SD10
SD9
SA4
DVDD
IO16
DATA/ADR#
SA8
SA5
SA6
SA7
SA9
DGND
INT
IOW#
AEN
IOWAIT
DVDD
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
RST
DGND
TEST1
TEST2
TEST3
TEST4
DVDD
X2_25M
X1_25M
DGND
NC
AGND
AVDD
AVDD
RX+
RX-
AGND
AGND
TXO+
TXO-
AVDD
DVDD
LINK_I
RXD0
RXD1
RXD2
RXD3
DGND
CRS
COL
RX_DV
RX_ER
RX_CLK
TEST5
TX_CLK
TXD0
TXD2
TXD3
TX_EN
DVDD
MDIO
MDC
DGND
CLK20MO
SPEED#
DUP#
LINKACT#
DGND
EEDI
EEDO
EECK
EECS
GPIO0
GPIO1
GPIO2
GPIO3
DVDD
DVDD
NC
NC
