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tps543820-ESR的 应该是输出电容的ESR
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TPS543820 具有内部补偿高级电流模式控制功能的 TPS543820 4V 至 18V 输入、
83668A 同步 SWIFT™ 降压转换器
1 特性
• 固定频率、内部补偿高级电流模式 (ACM) 控制
• 集成式 25mΩ 和 6.5mΩ MOSFET
• 输入电压范围:4V 至 18V
• 输出电压范围:0.5V 至 7V
• 三种可选的 PWM 斜坡选项,可优化控制环路性能
• 五种可选的开关频率:500kHz、750kHz、1MHz、
1.5MHz 和 2.2MHz
• 与一个外部时钟同步
• 0.5V,整个温度范围内的电压基准精度为 ±0.5%
• 可选的软启动时间:0.5ms、1ms、2ms 和 4ms
• 单调启动至预偏置输出
• 可选的电流限制,支持 8A 和 6A 运行
• 具有可调节输入欠压锁定功能的使能端
• 电源正常输出监视器
• 输出过压、输出欠压、输入欠压、过流和过热保护
• 与 TPS543620 和 TPS543320 引脚对引脚兼容
• –40°C 至 150°C 的工作结温范围
• 2.5mm × 3mm 14 引脚 VQFN-HR 封装,间距为
0.5mm
2 应用
• 无线基础设施和有线通信设备
• 光纤网络
• 测试和测量
• 医疗和保健
3 说明
TPS543820TPS543820 是一款高效的 18V、8A 同
步降压转换器,其中采用了内部补偿固定频率高级电流
模式控制。该器件能够在以高达 2.2MHz 的开关频率
运行时提供高效率。
™
该器件采用 2.5mm × 3mm 小
型 HotRod VQFN 封装,并且在高频率下具有很高的效
率,因此成为需要小解决方案尺寸的设计的理想选择。
固定频率控制器可以在 500kHz 至 2.2MHz 范围内运
行,并且可以通过 SYNC 引脚与外部时钟同步。其他
功能包括高精度电压基准、可选的软启动时间、单调启
动至预偏置输出、可选的电流限制、可调 UVLO(通过
EN 引脚实现)以及全套故障保护。
器件信息
器件型号 封装
(1)
封装尺寸(标称值)
TPS543820 VQFN-HR (14) 2.50mm x 3.00mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
TPS543820
EN
MODE
FB
BOOT
SW
PGOOD
VIN
SYNC/FSEL
PGND
BP5
AGND
V
OUT
V
IN
SW
简化版原理图
Output Current (A)
Efficiency (%)
0 1 2 3 4 5 6 7 8
60
64
68
72
76
80
84
88
92
96
100
12 V to 0.8 V, 1 MHz
12 V to 1 V, 1 MHz
12 V to 1.2 V, 1 MHz
12 V to 1.8 V, 1 MHz
效率
TPS543820
ZHCSLZ3B – MAY 2020 – REVISED JUNE 2021
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLUSED1
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................4
6.5 Electrical Characteristics ............................................5
6.6 Typical Characteristics................................................ 7
7 Detailed Description........................................................9
7.1 Overview..................................................................... 9
7.2 Functional Block Diagram........................................... 9
7.3 Feature Description.....................................................9
7.4 Device Functional Modes..........................................16
8 Application and Implementation.................................. 17
8.1 Application Information............................................. 17
8.2 Typical Applications.................................................. 17
9 Power Supply Recommendations................................34
10 Layout...........................................................................35
10.1 Layout Guidelines................................................... 35
10.2 Layout Example...................................................... 35
11 Device and Documentation Support..........................37
11.1 接收文档更新通知................................................... 37
11.2 支持资源..................................................................37
11.3 Trademarks............................................................. 37
11.4 Electrostatic Discharge Caution.............................. 37
11.5 术语表..................................................................... 37
12 Mechanical, Packaging, and Orderable
Information.................................................................... 38
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision A (February 2021) to Revision B (June 2021) Page
• Changed 10-ns transient to 20-ns transient........................................................................................................4
• Changed VIN to SW, transient 20 ns min value to -6......................................................................................... 4
• Changed SW, transient 20 ns min value to -5.................................................................................................... 4
• Added T
OFF(min)
max value................................................................................................................................. 5
• Added text for considering minimum off-time for fsw selection.........................................................................18
Changes from Revision * (December 2020) to Revision A (February 2021) Page
• Changed max V
OUT
to 7 V..................................................................................................................................4
TPS543820
ZHCSLZ3B – MAY 2020 – REVISED JUNE 2021
www.ti.com.cn
2 Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TPS543820
5 Pin Configuration and Functions
SW
VIN
PGND
BOOT
SW
VIN
PGND
AGND
MODE
SYNC/
FSEL
FB
BP5
PGOOD
1
234
5
6
7
8
9
10
11
12
13
14
EN
图 5-1. 14-Pin VQFN-HR RPY Package (Top View)
表 5-1. Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
SYNC/FSEL 1 I
Frequency select and external clock synchronization. A resistor to ground sets the switching
frequency of the device. An external clock can also be applied to this pin to synchronize the
switching frequency.
MODE 2 I A resistor to ground selects the current limit, soft start rate, and PWM ramp amplitude.
PGOOD 3 O Open-drain power good indicator
FB 4 I
Feedback pin for output voltage regulation. Connect this pin to the midpoint of a resistor
divider to set the output voltage.
AGND 5 - Ground return for internal analog circuits
BP5 6 O Internal 4.5-V regulator output. Bypass this pin with a 2.2-μF capacitor to AGND.
EN 7 I
Enable pin. Float to enable, enable/disable with an external signal, or adjust the input
undervoltage lockout with a resistor divider.
VIN 8, 12 I
Input power to the power stage. Low impedance bypassing of these pins to PGND is critical.
A 10-nF to 100-nF capacitor from each VIN to PGND close to IC is required.
PGND 9, 11 -
Ground return for the power stage. This pin is internally connected to the source of the
low-side MOSFET.
SW 10 O Switch node of the converter. Connect this pin to the output inductor.
SW 13 O
Return path for the internal high-side MOSFET gate driver bootstrap capacitor. Connect a
capacitor from BOOT to this pin. The SW pins are connected internally.
BOOT 14 I
Supply for the internal high-side MOSFET gate driver. Connect a capacitor from this pin to
SW.
www.ti.com.cn
TPS543820
ZHCSLZ3B – MAY 2020 – REVISED JUNE 2021
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: TPS543820
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN MAX UNIT
Input voltage VIN -0.3 20 V
Input voltage VIN to SW, DC -0.3 20 V
Input voltage VIN to SW, transient 20 ns -6 25 V
Input voltage BOOT -0.3 25 V
Input voltage BOOT to SW -0.3 6 V
Input voltage EN, PGOOD, MODE, SYNC/FSEL, FB -0.3 6 V
Output voltage SW, DC -0.3 20 V
Output voltage SW, transient 20 ns -5 22 V
Operating junction
temperature, T
J
Operating junction temperature, T
J
-40 150 °C
Storage temperature, T
stg
–55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE UNIT
V
(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001
(1)
±2000 V
V
(ESD)
Electrostatic discharge
Charged-device model (CDM), per JEDEC specification
JESD22-C101
(2)
±500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Input voltage V
IN
4 18 V
Output voltage V
OUT
0.5 7 V
Output current I
OUT
8 A
T
J
Operating junction temperature -40 150 °C
f
SYNC
External clock frequency 400 2600 kHz
6.4 Thermal Information
THERMAL METRIC
(1)
TPS543820
UNITRPY (QFN, JEDEC) RPY (QFN, TI EVM)
14 PINS 14 PINS
R
θJA
Junction-to-ambient thermal resistance 58.9 29.1 °C/W
R
θJC(top)
Junction-to-case (top) thermal resistance 37.8 Not applicable
(2)
°C/W
R
θJB
Junction-to-board thermal resistance 7.3 Not applicable
(2)
°C/W
ψ
JT
Junction-to-top characterization parameter 0.9 1.8 °C/W
ψ
JB
Junction-to-board characterization parameter 7.2 13.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Not applicable to an EVM layout.
TPS543820
ZHCSLZ3B – MAY 2020 – REVISED JUNE 2021
www.ti.com.cn
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TPS543820
6.5 Electrical Characteristics
T
J
= –40 °C to +150°C, V
VIN
= 4 V - 18 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE
I
Q(VIN)
VIN operating non-switching supply current
V
EN
= 1.3 V, V
FB
= 550 mV, V
VIN
= 12 V, 1
MHz
1200 1600 µA
I
SD(VIN)
VIN shutdown supply current V
EN
= 0 V, V
VIN
= 12 V 15 25 µA
VIN UVLO rising threshold VIN rising 3.9 4 4.1 V
VIN UVLO hysteresis 150 mV
ENABLE AND UVLO
V
EN(rise)
EN voltage rising threshold EN rising, enable switching 1.2 1.25 V
V
EN(fall)
EN voltage falling threshold EN falling, disable switching 1.05 1.1 V
V
EN(hyst)
EN voltage hysteresis 100 mV
EN pin sourcing current V
EN
= 1.1 V 0.4 1.5 µA
EN pin sourcing current V
EN
= 1.3 V 11.6 µA
INTERNAL LDO BP5
V
BP5
Internal LDO BP5 output voltage V
VIN
= 12 V 4.5 V
BP5 dropout voltage V
VIN
– V
BP5
, V
VIN
= 3.8 V 350 mV
BP5 short-circuit current limit V
VIN
= 12 V 75 mA
REFERENCE VOLTAGE
V
FB
Feedback Voltage T
J
= –40°C to 150°C 497.5 500 502.5 mV
I
FB(LKG)
Input leakage current into FB pin
V
FB
= 500 mV, non-switching, V
VIN
= 12 V,
V
EN
= 0 V
1 nA
SWITCHING FREQUENCY AND OSCILLATOR
f
SW
Switching frequency R
MODE
= 24.3 kΩ 450 500 550 kHz
f
SW
Switching frequency R
MODE
= 17.4 kΩ 675 750 825 kHz
f
SW
Switching frequency R
MODE
= 11.8 kΩ 900 1000 1100 kHz
f
SW
Switching frequency R
MODE
= 8.06 kΩ 1350 1500 1650 kHz
f
SW
Switching frequency R
MODE
= 4.99 kΩ 1980 2200 2420 kHz
SYNCHRONIZATION
V
IH(sync)
High-level input voltage 1.8 V
V
IL(sync)
Low-level input voltage 0.8 V
SOFT-START
t
SS1
Soft-start time R
MODE
= 1.78 kΩ 0.5 ms
t
SS2
Soft-start time R
MODE
= 2.21 kΩ 1 ms
t
SS3
Soft-start time R
MODE
= 2.74 kΩ 2 ms
t
SS4
Soft-start time R
MODE
= 3.32 kΩ 4 ms
POWER STAGE
R
DS(on)HS
High-side MOSFET on-resistance T
J
= 25°C, V
VIN
= 12 V, V
BOOT-SW
= 4.5 V 25 mΩ
R
DS(on)LS
Low-side MOSFET on-resistance T
J
= 25°C, V
BP5
= 4.5 V 6.5 mΩ
V
BOOT-SW(UV_r)
BOOT-SW UVLO rising threshold V
BOOT-SW
rising 3.2 V
V
BOOT-SW(UV_f)
BOOT-SW UVLO falling threshold V
BOOT-SW
falling 2.8 V
T
ON(min)
Minimum ON pulse width I
OUT
> ½ I
L_PK-PK
30 37 ns
T
OFF(min)
Minimum OFF pulse width
(1)
115 140 ns
CURRENT SENSE AND OVERCURRENT PROTECTION
I
OC_HS_pk1
High-side peak current limit R
MODE
= 1.78 kΩ 11.7 12.2 12.7 A
I
OC_HS_pk2
High-side peak current limit R
MODE
= 22.1 kΩ 8.6 9 9.6 A
I
OC_LS_src1
Low-side sourcing current limit R
MODE
= 1.78 kΩ 9.4 10.4 11.3 A
I
OC_LS_src2
Low-side sourcing current limit R
MODE
= 22.1 kΩ 6.2 7.4 8.5 A
I
OC_LS_snk
Low-side sinking current limit Current into SW pin 2.95 A
OUTPUT OVERVOLTAGE AND UNDERVOLTAGE PROTECTIONS
V
OVP
Overvoltage-protection (OVP) threshold
voltage
V
FB
rising 120 % V
REF
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TPS543820
ZHCSLZ3B – MAY 2020 – REVISED JUNE 2021
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: TPS543820
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