Terms
• Fundamental Reset: contains Cold Reset and Warm Reset. Normaly use PERST#
• Hot Reset: Hot Reset is a software generated reset by downstream port. Is reach by receiving two consecutive TS1 Ordered Sets with the Hot Reset
bit assert.
• Bit Lock: when the receiver PLL locks on to the Tx Clock frequency , the receiver is said to achieve “Bit Lock” receiver use Ts1/TS2/FTS 0/1 transition
to do bit lock.
• Symbol Lock: the Deserializer know how to distinguish a valid 10-bit symbol is said symbol lock. The 10-bit COM(K28.5) symbol used for COM
detector(which looks for two consecutive 0s or 2 consecutive 1s followed by a string of five 1s or five 0s) to do symbol lock.
• Electrical Idle: the transmitter D+ and D- voltage are held at a steady, constant voltage. this state is used in power saving states such as L0s, L1, Link
inactive, or Link disable states.
• Logical Idle: A period of one or more Symbol Times when no information (TLPs, DLLPs, or any special Symbol) is being transmitted or received. Unlike
Electrical Idle,during Logical Idle the idle data Symbol is being transmitted and received
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